User`s manual

Using the Verilog PLI
5-88 Verilog Simulation ModelSim Xilinx User’s Manual
% cc -c -I<install_dir>/modeltech/include veriuser.c
% ld -G -o app.sl veriuser.o libapp.a
That’s all there is to it. The PLI application is ready to be run with ModelSim
Verilog. All that’s left is to specify the resulting object file to the simulator for
loading using the Veriuser modesim.ini file entry, the -pli simulator option, or the
PLIOBS environment variable (see "Registering PLI applications").
Note: On the HP700 platform, the object files must be compiled as position-independent code by using the
+z compiler option. Since, the object files supplied for Verilog-XL may be compiled for static linking, you
may not be able to use the object files to create a dynamically loadable object for ModelSim Verilog. In this
case, you must get the third party application vendor to supply the object files compiled as position-
independent code.
Support for VHDL objects
The PLI ACC routines also provide limited support for VHDL objects in a mixed
VHDL/Verilog design. The following table lists the VHDL objects for which
handles may be obtained and their type and fulltype constants:
Type Fulltype Description
accArchitecture accArchitecture instantiation of an architecture
accArchitecture accEntityVitalLevel0 instantiation of an architecture whose entity is
marked with the attribute VITAL_Level0
accArchitecture accArchVitalLevel0 instantiation of an architecture which is marked
with the attribute VITAL_Level0
accArchitecture accArchVitalLevel1 instantiation of an architecture which is marked
with the attribute VITAL_Level1
accArchitecture accForeignArch instantiation of an architecture which is marked
with the attribute FOREIGN and which does not
contain any VHDL statements or objects other than
ports and generics
accArchitecture accForeignArchMixed instantiation of an architecture which is marked
with the attribute FOREIGN and which contains
some VHDL statements or objects besides ports
and generics