User`s manual

Using the Verilog PLI
5-86 Verilog Simulation ModelSim Xilinx User’s Manual
reason_interactive
For the execution of the $stop system task or any other time the simulation is interrupted
and waiting for user input.
reason_scope
For the execution of the environment command or selecting a scope in the structure
window. Also for the call to acc_set_interactive_scope if the callback_flag argument is
non-zero.
reason_paramvc
For the change of value on the system task or function argument.
reason_synch
For the end of time step event scheduled by tf_synchronize.
reason_rosynch
For the end of time step event scheduled by tf_rosynchronize.
reason_reactivate
For the simulation event scheduled by tf_setdelay.
reason_paramdrc
Not supported in ModelSim Verilog.
reason_force
Not supported in ModelSim Verilog.
reason_release
Not supported in ModelSim Verilog.
reason_disable
Not supported in ModelSim Verilog.
The sizetf callback function
A user-defined system function specifies the width of its return value with the
sizetf callback function, and the simulator calls this function while loading the
design. The following details on the sizetf callback function are not found in the
IEEE Std 1364:
• If you omits the sizetf function, then a return width of 32 is assumed.