User`s manual

Using the Verilog PLI
5-80 Verilog Simulation ModelSim Xilinx Users Manual
protect
remove_gatenames
remove_netnames
suppress_faults
The following Verilog-XL compiler directives produce warning messages in
ModelSim Verilog. These are not implemented in ModelSim Verilog, and any
code containing these directives may behave differently in ModelSim Verilog than
in Verilog-XL.
default_decay_time
default_trireg_strength
signed
unsigned
Using the Verilog PLI
The Verilog PLI provides a mechanism for defining system tasks and functions
that communicate with the simulator through a C procedural interface. There are
many third party applications available that interface to Verilog simulators
through the PLI interface (see Third party PLI applications
(5-87)). In addition,
you may write your own PLI applications.
ModelSim Verilog implements the PLI as defined in the IEEE Std 1364, with the
exception of the VPI routines and the acc_handle_datapath routine. Currently, the
VPI routines are not commonly used, although ModelSim will support them in a
future release. The acc_handle_datapath routine is not implemented because the
information it returns is more appropriate for a static timing analysis tool.
The IEEE Std 1364 is the reference that defines the usage of the PLI routines. This
manual only describes details of using the PLI with ModelSim Verilog.
Registering PLI applications
Each PLI application must register its system tasks and functions with the
simulator, providing the name of each system task and function and the associated
callback routines. Since many PLI applications already interface to Verilog-XL,
ModelSim Verilog PLI applications make use of the same mechanism to register
information about each system task and function in an array of s_tfcell structures.
This structure is declared in the veriuser.h include file as follows:
typedef int (*p_tffn)();
typedef struct t_tfcell {
short type;/* USERTASK, USERFUNCTION, or USERREALFUNCTION */
short data;/* passed as data argument of callback function */