User`s manual

Compiler Directives
ModelSim Xilinx User’s Manual Verilog Simulation 5-79
‘unconnected_drive
‘undef
Verilog-XL compatible compiler directives
The following compiler directives are provided for compatibility with Verilog-
XL.
‘delay_mode_distributed
This directive disables path delays in favor of distributed delays. See
Delay modes
(5-71) for details.
‘delay_mode_path
This directive sets distributed delays to zero in favor of path delays. See
Delay modes
(5-71) for details.
‘delay_mode_unit
This directive sets path delays to zero and non-zero distributed delays to
one time unit. See Delay modes
(5-71) for details.
‘delay_mode_zero
This directive sets path delays and distributed delays to zero. See Delay
modes
(5-71) for details.
‘uselib
This directive is an alternative to the -v, -y, and +libext source library
compiler options. See Verilog-XL ‘uselib compiler directive
(5-63) for
details.
The following Verilog-XL compiler directives are silently ignored by ModelSim
Verilog. Many of these directives are irrelevant to ModelSim Verilog, but may
appear in code being ported from Verilog-XL.
‘accelerate
‘autoexpand_vectornets
‘disable_portfaults
‘enable_portfaults
‘endprotect
‘expand_vectornets
‘noaccelerate
‘noexpand_vectornets
‘noremove_gatenames
‘noremove_netnames
‘nosuppress_faults