User`s manual

Compiler Directives
5-78 Verilog Simulation ModelSim Xilinx User’s Manual
Compiler Directives
ModelSim Verilog supports all of the compiler directives defined in the IEEE Std
1364-1995 and some additional Verilog-XL compiler directives for compatibility.
Many of the compiler directives (such as ‘define and ‘timescale) take effect at the
point they are defined in the source code and stay in effect until the directive is
redefined or until it is reset to its default by a ‘resetall directive. The effect of
compiler directives spans source files, so the order of source files on the
compilation command line may be significant. For example, if you have a file that
defines some common macros for the entire design, then you may need to place it
first in the list of files to be compiled.
The ‘resetall directive affects only the following directives by resetting them back
to their default settings (this information is not provided in the IEEE Std 1364-
1995):
‘celldefine
‘define_nettype
‘delay_mode_distributed
‘delay_mode_path
‘delay_mode_unit
‘delay_mode_zero
‘timescale
‘unconnected_drive
‘uselib
ModelSim Verilog implicitly defines the following macro:
‘define MODEL_TECH
IEEE Std 1364-1995 compiler directives
The following compiler directives are described in detail in the IEEE Std 1364-
1995; however, the ‘define directive is not fully implemented as described - it
does not support macro arguments.
‘celldefine
‘default_nettype
‘define
‘else
‘endcelldefine
‘endif
‘ifdef
‘include
‘nounconnected_drive
‘resetall
‘timescale