User`s manual

System Tasks
ModelSim Xilinx User’s Manual Verilog Simulation 5-75
Verilog-XL compatible system tasks
The following system tasks are provided for compatibility with Verilog-XL.
Although they are not part of the IEEE standard, they are described in an annex of
the IEEE Std 1364-1995.
$countdrivers
$getpattern
$sreadmemb
$sreadmemh
The following system tasks are also provided for compatibility withVerilog-XL,
but they are not described in the IEEE Std 1364-1995.
$sdf_annotate
See: The $sdf_annotate system task (8-222)
$test$plusargs("plus argument")
This system function tests for the presence of a specific plus argument on the
simulator’s command line. It returns 1 if the plus argument is present;
otherwise, it returns 0. For example, to test for +verbose:
if ($test$plusargs("verbose"))
$display("Executing cycle 1");
$removal(reference_event, data_event, limit, [notifier])
The $removal timing check issues a timing violation under the following
condition:
0 < ((time of reference event) - (time of data event)) < limit
$recrem(reference_event, data_event, recovery_limit, removal_limit, [notifier],
[tstamp_cond], [tcheck_cond], {delayed-reference], [delayed_data])
The $recrem timing check is a combined $recovery and $removal timing
check. It behaves very much like the $setuphold timing check, along with the
extensions for negative constraints and an alternate method of conditioning
(see the description of $setuphold below)
The following system tasks are extended to provide additional functionality for
negative timing constraints and an alternate method of conditioning, as does
Verilog-XL.
$setuphold(clk_event, data_event, setup_limit, hold_limit, [notifier],
[tstamp_cond], [tcheck_cond], [delayed_clk], [delayed_data])