User`s manual

Cell Libraries
ModelSim Xilinx User’s Manual Verilog Simulation 5-71
Cell Libraries
Model Technology is the first Verilog simulation vendor to pass the ASIC
Council’s Verilog test suite and achieve the "Library Tested and Approved"
designation from Si2 Labs. This test suite is designed to ensure Verilog timing
accuracy and functionality and is the first significant hurdle to complete on the
way to achieving full ASIC vendor support. As a consequence, many ASIC and
FPGA vendors’ Verilog cell libraries are compatible with ModelSim Verilog.
The cell models generally contain Verilog "specify blocks" that describe the path
delays and timing constraints for the cells. See section 13 in the IEEE Std 1364-
1995 for details on specify blocks, and section 14.5 for details on timing
constraints. ModelSim Verilog fully implements specify blocks and timing
constraints as defined in the IEEE Std 1364-1995 along with some Verilog-XL
compatible extensions.
SDF timing annotation
ModelSim Verilog supports timing annotation from Standard Delay Format (SDF)
files. See Chapter 8 - Standard Delay Format (SDF) Timing Annotation for
details.
Delay modes
Verilog models may contain both distributed delays and path delays. The delays
on primitives, UDPs, and continuous assignments are the distributed delays,
whereas the port-to-port delays specified in specify blocks are the path delays.
These delays interact to determine the actual delay observed. Most Verilog cells
use path delays exclusively, with the distributed delays set to zero. For example,
module and2(y, a, b);
input a, b;
output y;
and(y, a, b);
specify
(a => y) = 5;
(b => y) = 5;
endspecify
endmodule
In the above two-input "and" gate cell, the distributed delay for the "and" primitive
is zero, and the actual delays observed on the module ports are taken from the path
delays. This is typical for most cells, but a complex cell may require non-zero