User`s manual

Simulation
5-68 Verilog Simulation ModelSim Xilinx Users Manual
A WRITE/READ or READ/WRITE hazard is flagged even if the write does not
modify the variable's value.
Glitches on nets caused by non-guaranteed event ordering are not detected.
Verilog-XL compatible simulator options
See vsim (CR-148) for a complete list of simulator options. The options described
here are equivalent to Verilog-XL options. Many of these are provided to ease the
porting of a design to ModelSim Verilog.
+alt_path_delays
Specify path delays operate in inertial mode by default. In inertial mode, a pending
output transition is cancelled before a new output transition is scheduled, and the
delay is selected based on the transition from the current value of the net to the
new pending value. The result is that an output may have no more than one
pending transition at a time, and that pulses narrower than the delay are filtered.
The +alt_path_delays option modifies the inertial mode such that a delay is based
on a transition from a pending output value rather than the current value of the net.
This option has no effect in transport mode (see +pulse_e
(5-69) and +pulse_r (5-
70)
).
-l <filename>
By default, the simulation log is written to the file "transcript". The -l option
allows you to specify an alternate file.
+maxdelays
This option selects the maximum value in min:typ:max expressions. The default
is the typical value. This option has no effect if the min:typ:max selection was
determined at compile time.
+mindelays
This option selects the minimum value in min:typ:max expressions. The default is
the typical value. This option has no effect if the min:typ:max selection was
determined at compile time.
+no_notifier
This option disables the toggling of the notifier register argument of the timing
check system tasks. By default, the notifier is toggled when there is a timing check
violation, and the notifier usually causes a UDP to propagate an X. Therefore, the
+no_notifier option suppresses X propagation on timing violations.