User`s manual

Compilation
ModelSim Xilinx User’s Manual Verilog Simulation 5-63
Verilog-XL ‘uselib compiler directive
The ‘uselib compiler directive is an alternative source library management
scheme to the -v, -y, and +libext compiler options. It has the advantage that a
design may reference different modules having the same name. The ‘uselib
compiler directive is not defined in the IEEE Std 1364-1995, but ModelSim
supports it for compatibility with Verilog-XL.
The syntax for the ‘uselib directive is:
‘uselib <library_reference>...
where <library_reference> is:
dir=<library_directory> | file=<library_file> | libext=<file_extension> |
lib=<library_name>
In Verilog-XL, the library references are equivalent to command line options as
follows:
dir=<library_directory> -y <library_directory>
file=<library_file> -v <library_file>
libext=<file_extension> +libext+<file_extension>
For example, the following directive
‘uselib dir=/h/vendorA libext=.v
is equivalent to the following command line options:
-y /h/vendorA +libext+.v
Since the ‘uselib directives are embedded in the Verilog source code, there is
more flexibility in defining the source libraries for the instantiations in the design.
The appearance of a ‘uselib directive in the source code explicitly defines how
instantiations that follow it are resolved, completely overriding any previous
‘uselib directives.
For example, the following code fragment shows how two different modules that
have the same name can be instantiated within the same design:
‘uselib dir=/h/vendorA file=.v
NAND2 u1(n1, n2, n3);
‘uselib dir=/h/vendorB file=.v
NAND2 u2(n4, n5, n6);
This allows the NAND2 module to have different definitions in the vendorA and
vendorB libraries.