User`s manual

Compilation
5-62 Verilog Simulation ModelSim Xilinx User’s Manual
+libext+<suffix>
This option works in conjunction with the -y option. It specifies file extensions for
the files in a source library directory. By default the compiler searches for files
without extensions. If you specify the +libext option, then the compiler will
search for a file with the suffix appended to an unresolved name. You may specify
only one +libext option, but it may contain multiple suffixes separated by "+". The
extensions are tried in the order they appear in the +libext option.
+librescan
This option changes how unresolved references are handled that are added while
compiling a module or UDP from a source library. By default, the compiler
attempts to resolve these references as it continues searching the source libraries.
If you specify the +librescan option, then the new unresolved references are
deferred until after the current pass through the source libraries. They are then
resolved by searching the source libraries from the beginning in the order they are
specified on the command line.
+nolibcell
By default, all modules compiled from a source library are treated as though they
contain a ‘celldefine compiler directive. This option disables this default. The
‘celldefine directive only affects the PLI Access routines acc_next_cell and
acc_next_cell_load.
-R <simargs>
This option instructs the compiler to invoke the simulator after compiling the
design. The compiler automatically determines which top level modules are to be
simulated. The command line arguments following -R are passed to the simulator,
not the compiler. Place the -R option at the end of the command line or terminate
the simulator command line arguments with a single "-" character to differentiate
them from compiler command line arguments.
The -R option is not a Verilog-XL option, but it is used by ModelSim Verilog to
combine the compile and simulate phases together as you may be used to with
Verilog-XL. It is not recommended that you regularly use this option because you
will incur the unnecessary overhead of compiling your design for each simulation
run. Mainly, it is provided to ease the transition to ModelSim Verilog.