User`s manual

Compilation
5-58 Verilog Simulation ModelSim Xilinx User’s Manual
The following is an example of how to compile a design with automatic
incremental compilation:
% vlog -incr top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules:
top
Now, suppose that you modify the functionality of the "or2" module:
% vlog -incr top.v and2.v or2.v
-- Skipping module top
-- Skipping module and2
-- Compiling module or2
Top level modules:
top
The compiler informs you that it skipped the modules "top" and "and2", and
compiled "or2".
Automatic incremental compilation is intelligent about when to compile a module.
For example, adding a comment to your source code does not result in a
recompile; however, changing the compiler command line options results in a
recompile of all modules.
Library usage
All modules and UDPs in a Verilog design must be compiled into one or more
libraries. One library is usually sufficient for a simple design, but you may want
to organize your modules into various libraries for a complex design. If your
design uses different modules having the same name, then you are required to put
those modules in different libraries because design unit names must be unique
within a library.
The following is an example of how you may organize your ASIC cells into one
library and the rest of your design into another:
% vlib work
% vlib asiclib
% vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2