User`s manual

Compilation
ModelSim Xilinx User’s Manual Verilog Simulation 5-57
Compile the design in top down order (assumes work library already exists):
% vlog top.v
-- Compiling module top
Top level modules:
top
% vlog and2.v
-- Compiling module and2
Top level modules:
and2
% vlog or2.v
-- Compiling module or2
Top level modules:
or2
Note that the compiler lists each module as a top level module, although,
ultimately, only "top" is a top level module. If a module is not referenced by
another module compiled in the same invocation of the compiler, then it is listed
as a top level module. This is just an informative message and can be ignored
during incremental compilation. The message is more useful when you compile
an entire design in one invocation of the compiler and need to know the top level
module names for the simulator. For example,
% vlog top.v and2.v or2.v
-- Compiling module top
-- Compiling module and2
-- Compiling module or2
Top level modules:
top
The most efficient method of incremental compilation is to manually compile only
the modules that have changed. This is not always convenient, especially if your
source files have compiler directive interdependencies (such as macros). In this
case, you may prefer to always compile your entire design in one invocation of the
compiler. If you specify the -incr option, the compiler will automatically
determine which modules have changed and generate code only for those
modules. This is not as efficient as manual incremental compilation because the
compiler must scan all of the source code to determine which modules must be
compiled.