User`s manual

Compilation
5-56 Verilog Simulation ModelSim Xilinx User’s Manual
In this example, the simulator was run without the graphic interface by specifying
the -c option. After the design was loaded, the simulator command run -all was
entered, meaning to simulate until there are no more simulator events. Finally, the
quit command was entered to exit the simulator. By default, a log of the simulation
is written to the file "transcript" in the current directory.
Incremental compilation
By default, ModelSim Verilog supports incremental compilation of designs, thus
saving compilation time when you modify your design. Unlike other Verilog
simulators, there is no requirement that you compile the entire design in one
invocation of the compiler (although, you may do so if desired).
You are not required to compile your design in any particular order because all
module and UDP instantiations and external hierarchical references are resolved
when the design is loaded by the simulator. Incremental compilation is made
possible by deferring these bindings, and as a result some errors cannot be
detected during compilation. Commonly, these errors include: modules that were
referenced but not compiled, incorrect port connections, and incorrect hierarchical
references.
The following example shows how a hierarchical design can be compiled in top
down order:
Contents of top.v:
module top;
or2(n1, a, b);
and2(n2, n1, c);
endmodule
Contents of and2.v:
module and2(y, a, b);
output y;
input a, b;
and(y, a, b);
endmodule
Contents of or2.v:
module or2(y, a, b);
output y;
input a, b;
or(y, a, b);
endmodule