User`s manual

Compilation
ModelSim Xilinx User’s Manual Verilog Simulation 5-55
Compilation
Before you can simulate a Verilog design, you must first create a library and
compile the Verilog source code into that library. This section provides detailed
information on compiling Verilog designs. For information on creating a design
library, see Chapter 2 - Design Libraries.
ModelSim Verilog compiles Verilog source code into retargetable, executable
code, meaning that the library format is compatible across all supported platforms
and that you can simulate your design on any platform without having to
recompile your design specifically for that platform. As you compile your design,
the resulting object code for modules and UDPs is generated into a library. By
default, the compiler places results into the work library. You may specify an
alternate library with the -work option. The following is a simple example of how
to create a work library, compile a design, and simulate it:
Contents of top.v:
module top;
initial $display("Hello world");
endmodule
Create the work library:
% vlib work
Compile the design:
% vlog top.v
-- Compiling module top
Top level modules:
top
View the contents of the work library (optional):
% vdir
MODULE top
Simulate the design:
% vsim -c top
# Loading work.top
VSIM 1> run -all
# Hello world
VSIM 2> quit