User`s manual

5-54 Verilog Simulation ModelSim Xilinx User’s Manual
This chapter describes how to compile and simulate Verilog designs with
ModelSim Verilog. ModelSim Verilog implements the Verilog language as
defined by the IEEE Std 1364-1995, and it is recommended that you obtain this
specification as a reference manual.
In addition to the functionality described in the IEEE Std 1364-1995, ModelSim
Verilog includes the following features:
• Standard Delay Format (SDF) annotator compatible with many ASIC and
FPGA vendor's Verilog libraries.
• Value Change Dump (VCD) file extensions for ASIC vendor test tools.
• Dynamic loading of PLI applications.
• Compilation into retargetable, executable code.
• Incremental design compilation.
• Extensive support for mixing VHDL and Verilog in the same design (including
SDF annotation).
• Graphic Interface that is common with ModelSim VHDL.
• Extensions to provide compatibility with Verilog-XL.
The following IEEE Std 1364-1995 functionality is not implemented in ModelSim
Verilog:
• Array of instances (see section 7.1.5 in the IEEE Std 1364-1995).
• Verilog Procedural Interface (VPI) (see sections 22 and 23 in the IEEE Std
1364-1995).
• Macros (compiler `define directives) with arguments.
Many of the examples in this chapter are shown from the command line. For
compiling and simulation within ModelSim’s GUI see:
• Compiling with the graphic interface
(7-195)
• Simulating with the graphic interface (7-202)
ModelSim variables
Several variables are available to control simulation, provide simulator state
feedback, or modify the appearance of the ModelSim GUI. To take effect, some
variables, such as environment variables, must be set prior to simulation. See
Appendix A - ModelSim Variables for a complete listing of ModelSim variables.