User`s manual

TextIO implementation issues
4-50 VHDL Simulation ModelSim Xilinx User’s Manual
The ENDLINE function
The ENDLINE function described in the IEEE Standard VHDL Language
Reference Manual, IEEE Std 1076-1987 contains invalid VHDL syntax and
cannot be implemented in VHDL. This is because access types must be passed as
variables, but functions only allow constant parameters.
Based on an ISAC-VASG recommendation the ENDLINE function has been
removed from the TextIO package. The following test may be substituted for this
function:
(L = NULL) OR (L’LENGTH = 0)
The ENDFILE function
In the VHDL Language Reference Manuals, IEEE Std 1076-1987 and IEEE Std
1076-1993, the ENDFILE function is listed as:
-- function ENDFILE (L: in TEXT) return BOOLEAN;
As you can see, this function is commented out of the standard TextIO package.
This is because the ENDFILE function is implicitly declared, so it can be used
with files of any type, not just files of type TEXT.
Using alternative input/output files
You can use the TextIO package to read and write to your own files. To do this,
just declare an input or output file of type TEXT.
The VHDL’87 declaration is:
file
myinput : TEXT is in "pathname.dat";
For VHDL’93 the declaration is:
file
myinput : TEXT open read_mode is "pathname.dat";
Then include the identifier for this file ("myinput" in this example) in the
READLINE or WRITELINE procedure call.
Providing stimulus
You can create batch files containing force (CR-56) commands that provide
stimulus for simulation. A VHDL test bench has been included with the ModelSim
install files as an example; it illustrates how results can be generated by reading
vectors from a file. Check for this file:
<install_dir>/examples/stimulus.vhd