User`s manual

Using the TextIO package
ModelSim Xilinx User’s Manual VHDL Simulation 4-47
Using the TextIO package
To access the routines in TextIO, include the following statement in your VHDL
source code:
USE std.textio.all;
A simple example using the package TextIO is:
USE std.textio.all;
ENTITY simple_textio IS
END;
ARCHITECTURE simple_behavior OF simple_textio IS
BEGIN
PROCESS
VARIABLE i: INTEGER:= 42;
VARIABLE LLL: LINE;
BEGIN
WRITE (LLL, i);
WRITELINE (OUTPUT, LLL);
WAIT;
END PROCESS;
END simple_behavior;
Syntax for file declaration
The VHDL’87 syntax for a file declaration is:
file
identifier : subtype_indication is [ mode ] file_logical_name ;
where "file_logical_name" must be a string expression.
The VHDL’93 syntax for a file declaration is:
file
identifier_list : subtype_indication [ file_open_information ] ;
If a file is declared within an architecture, process, or package, the file is opened
when you start the simulator and is closed when you exit from it. If a file is
declared in a subprogram, the file is opened when the subprogram is called and
closed when execution RETURNs from the subprogram.
You can specify a full or relative path as the file_logical_name; for example
(VHDL’87):
file
filename : TEXT is in “usr\rick\myfile”;