User`s manual

Simulating VHDL designs
ModelSim Xilinx User’s Manual VHDL Simulation 4-45
VHDL version separately. The vcom (CR-106) command compiles units written
with version 1076 -1987 by default; use the -93 option with vcom
(CR-106) to
compile units written with version 1076 -1993. You can also change the default
by modifying the modelsim.ini file (see Chapter 3 - Projects and system
initialization for more information).
Dependency checking
Dependent design units must be reanalyzed when the design units they depend on
are changed in the library. vcom
(CR-106) determines whether or not the
compilation results have changed. For example, if you keep an entity and its
architectures in the same source file and you modify only an architecture and
recompile the source file, the entity compilation results will remain unchanged
and you will not have to recompile design units that depend on the entity.
Simulating VHDL designs
After compiling the design units, you can proceed to simulate your designs with
vsim
(CR-148). This section includes a discussion of simulation from the
Windows/DOS command line. You can also use the graphic interface for
simulation, see "Simulating with the graphic interface"
(7-202).
Note: Simulation normally stops if a failure occurs, however, if a bounds check on a signal fails the
simulator will continue running.
Invoking the simulator from the Main window
For VHDL, invoke vsim (CR-148) with the name of the configuration, or entity/
architecture pair. Note that if you specify a configuration you may not specify an
architecture.
This example invokes vsim
(CR-148) on the entity my_asic and the architecture
structure:
vsim my_asic structure
If a design unit name is not specified, vsim (CR-148) will present the Load Design
dialog box from which you can choose a configuration or entity/architecture pair.
See "Simulating with the graphic interface"
(7-202) for more information.