User`s manual

Compiling VHDL designs
4-44 VHDL Simulation ModelSim Xilinx User’s Manual
Compiling and simulating with the GUI
Many of the examples in this chapter are shown from the command line. For
compiling and simulation within ModelSim’s GUI see:
• Compiling with the graphic interface
(7-195)
• Simulating with the graphic interface (7-202)
ModelSim variables
Several variables are available to control simulation, provide simulator state
feedback, or modify the appearance of the ModelSim GUI. To take effect, some
variables, such as environment variables, must be set prior to simulation. See
Appendix A - ModelSim Variables for a complete listing of ModelSim variables.
Compiling VHDL designs
Creating a design library
Before you can compile your design, you must create a library to store the
compilation results. Use vlib
(CR-140) to create a new library. For example:
vlib work
This creates a library named work. By default, compilation results are stored in
the work library.
Note: The work library is actually a subdirectory named work. This subdirectory contains a special file
named _info. Do not create libraries using MS Windows or DOS commands – always use the vlib command
(CR-140).
See "Design Libraries"
(2-23) for additional information on working with libraries.
Invoking the VHDL compiler
ModelSim compiles one or more VHDL design units with a single invocation of
vcom
(CR-106), the VHDL compiler. The design units are compiled in the order
that they appear on the command line. For VHDL, the order of compilation is
important – you must compile any entities or configurations before an architecture
that references them.
You can simulate a design containing units written with both the 1076 -1987 and
1076 -1993 versions of VHDL. To do so you will need to compile units from each