User`s manual

ModelSim Xilinx User’s Manual VHDL Simulation 4-43
4 - VHDL Simulation
Chapter contents
Compiling VHDL designs . . . . . . . . . . . . . . . . . 44
Creating a design library . . . . . . . . . . . . . . . . 44
Invoking the VHDL compiler . . . . . . . . . . . . . . . 44
Dependency checking . . . . . . . . . . . . . . . . . 45
Simulating VHDL designs . . . . . . . . . . . . . . . . . 45
Invoking the simulator from the Main window. . . . . . . . . . . 45
Using the TextIO package . . . . . . . . . . . . . . . . . 47
Syntax for file declaration . . . . . . . . . . . . . . . . 47
Using STD_INPUT and STD_OUTPUT within ModelSim . . . . . . . 48
TextIO implementation issues . . . . . . . . . . . . . . . . 48
Writing strings and aggregates . . . . . . . . . . . . . . . 48
Reading and writing hexadecimal numbers . . . . . . . . . . . 49
Dangling pointers . . . . . . . . . . . . . . . . . . 49
The ENDLINE function . . . . . . . . . . . . . . . . 50
The ENDFILE function. . . . . . . . . . . . . . . . . 50
Using alternative input/output files . . . . . . . . . . . . . . 50
Providing stimulus . . . . . . . . . . . . . . . . . . 50
Obtaining the VITAL specification and source code . . . . . . . . . . 51
VITAL packages. . . . . . . . . . . . . . . . . . . . 51
ModelSim VITAL compliance . . . . . . . . . . . . . . . . 51
VITAL compliance checking . . . . . . . . . . . . . . . 52
Compiling and Simulating with accelerated VITAL packages. . . . . . . 52
Compiling and Simulating with accelerated VITAL packages . . . . . . . . 52
This chapter provides an overview of compilation and simulation for VHDL
designs within the ModelSim/PLUS environment, using the TextIO package with
ModelSim, and ModelSim’s implementation of the VITAL (VHDL Initiative
Towards ASIC Libraries) specification for ASIC modeling.
The TextIO package is defined within the VHDL Language Reference Manuals,
IEEE Std 1076-1987 and IEEE Std 1076-1993; it allows human-readable text
input from a declared source within a VHDL file during simulation.