User`s manual

Working with a Project
ModelSim Xilinx User’s Manual Projects and system initialization 3-41
Working with a Project
Open a project
First, you must have a project open to work with it. To open a project select File
> Open > Open Project from the Main window (cd’ing into projects directory
won’t work).
Once you have opened a project you can create HDL source files by selecting File
> New > New Source from the Main window. When you create HDL files in the
project’s root directory you are prompted to add them to the project. HDL files for
a given project must reside at or below the project’s root directory.
Compile a project
To compile your project’s HDL description with the project open, select Design >
Compile Project from the Main window, or click the Compile icon, and select the
files you want to compile. Each file will be compiled into your project’s work
library. Click Done when you are finished.
Simulating a project
To simulate an open project, select Design > Load New Design from the Main
window or click the Load Design icon. On the Design tab of this menu you specify
top level design unit for your project. On the VHDL and Verilog tabs you specify
HDL specific simulator settings (these are described in the VSIM portion of the
Reference Manual). On the SDF tab you can specify settings relating to the
annotation of design timing from an SDF file (optional).
Modifying a project
There are four types of project settings that can be modified; each is modified with
a different action:
1 Project-wide settings describe the make up of the project. These settings are changed
from the Options > Edit Project pull down menu.
2 Project compiler settings specify HDL compiler options. These settings are changed
from the Options > Compile pull down menu.