User`s manual

Modeling memory in VHDL
C-296 Tips and Techniques ModelSim Xilinx User’s Manual
data_out <= ram(address);
else
data_out <= ram(address);
end if;
end if;
end process;
end style_87;
architecture bad_style_87 of memory is
----------------------
signal ram : ram_type;
----------------------
begin
memory:
process (cs)
variable address : natural := 0;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = ’1’) then
ram(address) <= data_in;
data_out <= data_in;
else
data_out <= ram(address);
end if;
end if;
end process;
end bad_style_87;
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use std.standard.all;
library ieee;
use ieee.std_logic_1164.all;
package conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural;
function natural_to_sulv(n, bits : natural) return
std_ulogic_vector;
end conversions;
package body conversions is
function sulv_to_natural(x : std_ulogic_vector) return
natural is