User`s manual

Modeling memory in VHDL
ModelSim Xilinx User’s Manual Tips and Techniques C-295
architecture style_93 of memory is
------------------------------
shared variable ram : ram_type;
------------------------------
begin
memory:
process (cs)
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = ’1’) then
ram(address) := data_in;
data_out <= ram(address);
else
data_out <= ram(address);
end if;
end if;
end process memory;
-- illustrates a second process using the shared variable
initialize:
process (do_init)
variable address : natural;
begin
if rising_edge(do_init) then
for address in 0 to nwords-1 loop
ram(address) := data_in;
end loop;
end if;
end process initialize;
end architecture style_93;
architecture style_87 of memory is
begin
memory:
process (cs)
-----------------------
variable ram : ram_type;
-----------------------
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = ’1’) then
ram(address) := data_in;