User`s manual

Detecting infinite zero-delay loops
ModelSim Xilinx User’s Manual Tips and Techniques C-293
Detecting infinite zero-delay loops
VHDL simulation uses steps that advance simulated time, and steps that do not
advance simulated time. Steps that do not advance simulated time are called "delta
cycles". Delta cycles are used when signal assignments are made with zero time
delay.
If a large number of delta cycles occur without advancing time, it is usually a
symptom of an infinite zero-delay loop in the design. In order to detect the
presence of these loops, ModelSim defines a limit, the “iteration_limit", on the
number of successive delta cycles that can occur. When the iteration_limit is
exceeded, vsim stops the simulation and gives a warning message.
You can set the iteration_limit from the Simulation > Properties menu, or by
modifying the modelsim.ini file.
The iteration_limit default value is 1000.
When you get an iteration_limit warning, first increase the iteration limit and try
to continue simulation. If the problem persists, look for zero-delay loops.
One approach to finding zero-delay loops is to increase the iteration limit again
and start single stepping. You should be able to see the assignment statements or
processes that are looping. Looking at the Process window will also help you to
see the active looping processes.
When the loop is found, you will need to change the design to eliminate the
unstable loop.
See "Projects and system initialization"
(3-35) for more information on modifying
the modelsim.ini file.
Modeling memory in VHDL
As a VHDL user, you might be tempted to model a memory using signals. Two
common simulator problems are the likely result:
• You may get a "memory allocation error" message, which typically means the
simulator ran out of memory and failed to allocate more storage.
• Or, you may get very long load, elaboration or run times.
These problems are usually explained by the fact that signals consume a
substantial amount of memory (many dozens of bytes per bit), all of which needs
to be loaded or initialized before your simulation starts.