User`s manual

Tcl commands
ModelSim Xilinx User’s Manual Tcl and ModelSim 10-247
This feature allows VHDL variables and signals, and Verilog nets and registers to
be accessed using:
[examine -<radix> name]
The %name substitution is no longer supported. Everywhere %name could be
used, you now can use [examine -value -<radix> name] which allows the
flexibility of specifying command options. The radix specification is optional.
Command separator
A semicolon character (;) works as a separator for multiple commands on the same
line. It is not required at the end of a line in a command sequence.
Multiple-line commands
With Tcl, multiple-line commands can be used within macros and on the
command line. The command line prompt will change (as in a C shell) until the
multiple-line command is complete.
In the example below, note the way the opening brace { is at the end of the if and
else lines. This is important because otherwise the Tcl scanner won’t know that
there is more coming in the command and will try to execute what it has up to that
point, which won’t be what you intend.
if { [exa sig_a] == "0011ZZ"} {
echo "Signal value matches"
do macro_1.do
} else {
echo "Signal value fails"
do macro_2.do }
Evaluation order
An important thing to remember when using Tcl is that anything put in curly
brackets {} is not evaluated immediately. This is important for if-then-else,
procedures, loops, and so forth.