User`s manual

Troubleshooting
8-230 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
Troubleshooting
Several common mistakes in SDF annotation are outlined below.
Specifying the wrong instance
By far, the most common mistake in SDF annotation is to specify the wrong
instance to the simulator’s SDF options. The most common case is to leave off the
instance altogether, which is the same as selecting the top-level design unit. This
is almost always wrong because the instance paths in the SDF are relative to the
ASIC or FPGA model, which is usually instantiated under a top-level testbench.
A common example for both VHDL and Verilog test benches is provided below.
For simplicity, the test benches do nothing more than instantiate a model that has
no ports.
VHDL testbench
entity testbench is end;
architecture only of testbench is
component myasic
end component;
begin
dut : myasic;
end;
Verilog testbench
module testbench;
myasic dut();
endmodule
The name of the model is myasic and the instance label is dut. For either testbench,
an appropriate simulator invocation might be:
vsim -sdfmax /testbench/dut=myasic.sdf testbench
Optionally, you may leave off the name of the top-level:
vsim -sdfmax /dut=myasic.sdf testbench
The important point is to select the instance that the SDF is intended for. If the
model is deep within the design hierarchy, an easy way to find the instance name
is to first invoke the simulator without SDF options, open the structure window,
navigate to the model instance, select it, and enter the environment command
(CR-50). This command displays the instance name that should be used in the SDF
command-line option.