User`s manual

Verilog SDF
ModelSim Xilinx User’s Manual Standard Delay Format (SDF) Timing Annotation 8-225
SETUP is matched to $setup and $setuphold:
HOLD is matched to $hold and $setuphold:
SETUPHOLD is matched to $setup, $hold, and $setuphold:
RECOVERY is matched to $recovery:
REMOVAL is matched to $removal:
SDF Verilog
(SETUP d (posedge clk) (5)) $setup(d, posedge clk, 0);
(SETUP d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0);
SDF Verilog
(HOLD d (posedge clk) (5)) $hold(posedge clk, d, 0);
(HOLD d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0);
SDF Verilog
(SETUPHOLD d (posedge clk) (5) (5)) $setup(d, posedge clk, 0);
(SETUPHOLD d (posedge clk) (5) (5)) $hold(posedge clk, d, 0);
(SETUPHOLD d (posedge clk) (5) (5)) $setuphold(posedge clk, d, 0, 0);
SDF Verilog
(RECOVERY (negedge reset) (posedge clk) (5)) $recovery(negedge reset, posedge clk, 0);
SDF Verilog
(REMOVAL (negedge reset) (posedge clk) (5)) $removal(negedge reset, posedge clk, 0);