User`s manual

Verilog SDF
8-224 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
The IOPATH construct usually annotates path delays. If the module contains no
path delays, then all primitives that drive the specified output port are annotated.
INTERCONNECT and PORT are matched to input port:
Both of these constructs identify a module input or inout port and create an
internal net that is a delayed version of the port. This is called a Module Input Port
Delay (MIPD). All primitives, specify path delays, and specify timing checks
connected to the original port are reconnected to the new MIPD net.
PATHPULSE and GLOBALPATHPULSE are matched to specify path delays:
If the input and output ports are omitted in the SDF, then all path delays are
matched in the cell.
DEVICE is matched to primitives or specify path delays:
If the SDF cell instance is a primitive instance, then that primitive’s delay is
annotated. If it is a module instance, then all specify path delays are annotated that
drive the output port specified in the DEVICE construct (all path delays are
annotated if the output port is omitted). If the module contains no path delays, then
all primitives that drive the specified output port are annotated (or all primitives
that drive any output port if the output port is omitted).
SDF Verilog
(INTERCONNECT u1.y u2.a (5)) input a;
(PORT u2.a (5)) inout a;
SDF Verilog
(PATHPULSE a y (5) (10)) (a => y) = 0;
(GLOABLPATHPULSE a y (30) (60)) (a => y) = 0;
SDF Verilog
(DEVICE y (5)) and u1(y, a, b);
(DEVICE y (5)) (a => y) = 0; (b => y) = 0;