User`s manual

Verilog SDF
8-222 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
vsim -vital2.2b -sdfmax /testbench/u1=myasic.sdf testbench
For more information on resolving errors see "Troubleshooting" (8-230).
Verilog SDF
Verilog designs may be annotated using either the simulator command-line
options or the $sdf_annotate system task (also commonly used in other Verilog
simulators). The command-line options annotate the design immediately after it is
loaded, but before any simulation events take place. The $sdf_annotate task
annotates the design at the time that it is called in the Verilog source code. This
provides more flexibility than the command-line options.
The $sdf_annotate system task
The syntax for $sdf_annotate is:
Syntax
$sdf_annotate
(["<sdffile>"], [<instance>], ["<config_file>"], ["<log_file>"],
["<mtm_spec>"], ["<scale_factor>"], ["<scale_type>"]);
Arguments
"<sdffile>"
String that specifies the SDF file. Required.
<instance>
Hierarchical name of the instance to be annotated. Optional. Defaults to the instance where
the $sdf_annotate call is made.
"<config_file>"
String that specifies the configuration file. Optional. Currently not supported, this argument
is ignored.
"<log_file>"
String that specifies the logfile. Optional. Currently not supported, this argument is
ignored.
"<mtm_spec>"
String that specifies delay selection. Optional. The allowed strings are "minimum",
"typical", "maximum", and "tool_control". Case is ignored and the default is