User`s manual

VHDL VITAL SDF
8-220 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
warnings, or select Reduce SDF errors to warnings (-sdfnoerror) to change
errors to warnings.
See "Troubleshooting"
(8-230) for more information on errors and warnings, and
how to avoid them.
VHDL VITAL SDF
VHDL SDF annotation works on VITAL cells only. The IEEE 1076.4 VITAL
ASIC Modeling Specification describes how cells must be written to support SDF
annotation. Once again, the designer does not need to know the details of this
specification because the library provider has already written the VITAL cells and
tools that create compatible SDF files. However, the following summary is
provided to help understand simulator error messages in case of user error or in
case the vendor’s SDF does not match the VITAL cells. For additional VITAL
specification information see "Obtaining the VITAL specification and source
code"
(4-51).
SDF to VHDL generic matching
An SDF file contains delay and timing constraint data for cell instances in the
design. The annotator must locate the cell instances and the placeholders (VHDL
generics) for the timing data. Each type of SDF timing construct is mapped to the
name of a generic as specified by the VITAL modeling specification. The
annotator locates the generic and updates it with the timing value from the SDF
file. It is an error if the annotator fails to find the cell instance or the named
generic. The following are examples of SDF constructs and their associated
generic names:
SDF construct Matching VHDL generic name
(IOPATH a y (3)) tpd_a_y
(IOPATH (posedge clk) q (1) (2)) tpd_clk_q_posedge
(INTERCONNECT u1/y u2/a (5)) tipd_a
(SETUP d (posedge clk) (5)) tsetup_d_clk_noedge_posedge
(HOLD (negedge d) (posedge clk) (5)) thold_d_clk_negedge_posedge
(SETUPHOLD d clk (5) (5)) tsetup_d_clk & thold_d_clk