User`s manual

Specifying SDF files for simulation
8-218 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
SDF and ModelSim XE
For ModelSim XE, SDF timing annotation can only be applied to the Xilinx
libraries shown below; all other libraries will simulate without annotation. The
following mappings are defined in XE’s modelsim.ini file:
simprim = $MODEL_TECH/../xilinx/vhdl/simprim
logiblox = $MODEL_TECH/../xilinx/vhdl/logiblox
unisim = $MODEL_TECH/../xilinx/vhdl/unisim
unisim5K = $MODEL_TECH/../xilinx/vhdl/unisim5K
simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims
uni3000 = $MODEL_TECH/../xilinx/verilog/uni3000
unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
uni5200 = $MODEL_TECH/../xilinx/verilog/uni5200
uni9000 = $MODEL_TECH/../xilinx/verilog/uni9000
Specifying SDF files for simulation
ModelSim supports SDF versions 1.0 through 3.0. The simulator’s built-in SDF
annotator automatically adjusts to the version of the file. Use the following vsim
(CR-148) command-line options to specify the SDF files, the desired timing values,
and their associated design instances:
-sdfmin [<instance>=]<filename>
-sdftyp [<instance>=]<filename>
-sdfmax [<instance>=]<filename>
Any number of SDF files can be applied to any instance in the design by
specifying one of the above options for each file. Use -sdfmin to select minimum,
-sdftyp to select typical, and -sdfmax to select maximum timing values from the
SDF file.
Instance specification
The instance paths in the SDF file are relative to the instance that the SDF is
applied to. Usually, this instance is an ASIC or FPGA model instantiated under a
testbench. For example, to annotate maximum timing values from the SDF file
myasic.sdf to an instance u1 under a top-level named testbench, invoke the
simulator as follows:
vsim -sdfmax /testbench/u1=myasic.sdf testbench
If the instance name is omitted then the SDF file is applied to the top-level. This
is usually incorrect because in most cases the model is instantiated under a
testbench or within a larger system level simulation. In fact, the design may have