User`s manual

ModelSim Xilinx User’s Manual Standard Delay Format (SDF) Timing Annotation 8-217
8 - Standard Delay Format (SDF) Timing Annotation
Chapter contents
SDF and ModelSim XE . . . . . . . . . . . . . . . . . 218
Specifying SDF files for simulation . . . . . . . . . . . . . . 218
Instance specification . . . . . . . . . . . . . . . . 218
SDF specification with the GUI . . . . . . . . . . . . . 219
Errors and warnings. . . . . . . . . . . . . . . . . 219
VHDL VITAL SDF . . . . . . . . . . . . . . . . . . 220
SDF to VHDL generic matching . . . . . . . . . . . . . 220
Resolving errors. . . . . . . . . . . . . . . . . . 221
Verilog SDF . . . . . . . . . . . . . . . . . . . . 222
The $sdf_annotate system task . . . . . . . . . . . . . . 222
SDF to Verilog construct matching. . . . . . . . . . . . . 223
Optional edge specifications . . . . . . . . . . . . . . 227
Optional conditions . . . . . . . . . . . . . . . . . 228
Rounded timing values . . . . . . . . . . . . . . . . 229
SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . 229
Interconnect delays . . . . . . . . . . . . . . . . . . 229
Troubleshooting . . . . . . . . . . . . . . . . . . . 230
Obtaining the SDF specification. . . . . . . . . . . . . . . 232
This chapter discusses ModelSim’s implementation of SDF (Standard Delay
Format) timing annotation. Included are sections on VITAL SDF and Verilog
SDF, plus troubleshooting.
Verilog and VHDL VITAL timing data may be annotated from SDF files by using
the simulator’s built-in SDF annotator.
Note: Please see "SDF and ModelSim XE" (8-218) for ModelSim XE-specific information about SDF.