User`s manual

What is an "HDL item"
ModelSim Xilinx Users Manual Introduction 1-21
What is an "HDL item"
Because ModelSim works with both VHDL and Verilog, HDL refers to either
VHDL or Verilog when a specific language reference is not needed. Depending
on the context, HDL item can refer to any of the following:
VHDL block statement, component instantiation, constant, generate statement, generic, package,
signal, or variable
Verilog function, module instantiation, named fork, named begin, net, task, or register variable