User`s manual

Structure window
7-158 ModelSim XE Graphic Interface ModelSim Xilinx User’s Manual
Structure window
The Structure window provides a hierarchical view of the structure of your design.
An entry is created by each HDL item within the design. (Your design structure
can remain hidden if you wish, see "Source code security and -nodebug"
(C-292).)
HDL items you can view
The following HDL items for VHDL and
Verilog are represented by hierarchy within
Structure window.
VHDL items
(indicated by a dark blue square icon)
signals, variables, component instantiation,
generate statement, block statement, and
package
Verilog items
(indicated by a lighter blue circle icon)
parameters, registers, nets, module
instantiation, named fork, named begin, task,
and function
Virtual items
(indicated by an orange diamond icon)
virtual signals, buses, and functions, see
"Virtual Objects (User-defined buses, and
more)"
(6-100) for more information.
You can expand and contract the display to
view the hierarchical structure by clicking on
the boxes that contain "+" or "-". Clicking "+"
expands the hierarchy so the sub-elements of
that item can be seen. Clicking "-" contracts the hierarchy.
The first line of the Structure window indicates the top-level design unit being
simulated. By default, this is the only level of the hierarchy that is expanded upon
opening the Structure window.