User`s manual

Signals window
ModelSim Xilinx User’s Manual ModelSim XE Graphic Interface 7-151
Defining clock signals
Selecting Clock from the
Edit menu allows you to
define clock signals by
Name, Period, Duty Cycle,
Offset, and whether the
first rising edge is rising or
falling.
For clock signals starting
on the rising edge, the
definition for Period,
Offset, and Duty Cycle is
as follows:
If the signal type is std_logic, std_ulogic, bit, verilog wire, verilog net, or any
other logic type where 1 and 0 are valid, then 1 is the default High Value and 0 is
the default Low Value. For other signal types, you will need to specify a High
Value and a Low Value for the clock.
Period
Offset
High Time
Low Value
High Value
Duty Cycle = High Time/Period