User`s manual

Virtual Objects (User-defined buses, and more)
6-102 Multiple logfiles, datasets and virtuals ModelSim Xilinx User’s Manual
whose definition is stored in a special location, and is not visible in the Signals
window or to the normal virtual commands.
All other virtual signals are considered "explicit virtuals".
Virtual functions
Virtual functions behave in the GUI like signals but are not aliases of
combinations or elements of signals logged by the kernel. They consist of logical
operations on logged signals and may be dependent on simulation time. They may
be displayed in the Signals, Wave or List windows, accessed by the examine
command, but cannot be set by the force command.
Examples of virtual functions include the following:
• a function defined as the inverse of a given signal
• a function defined as the exclusive-OR of two signals
• a function defined as a repetitive clock
• a virtual function defined as "the rising edge of CLK delayed by 1.34 ns"
Virtual functions can also be used to convert signal types and map signal values.
The result type of a virtual signal can be any of the types supported in the GUI
expression syntax: integer, real, boolean, std_logic, std_logic_vector, and arrays
and records of these types. Verilog types are converted to VHDL 9-state std_logic
equivalents and Verilog net strengths are ignored.
Virtual functions can be created using the virtual function command (see below).
Virtual functions are also implicitly created by ModelSim when referencing bit-
selects or part-selects of Verilog registers in the GUI, or when expanding Verilog
registers in the Signals, Wave or List windows. This is necessary because
referencing Verilog register elements requires an intermediate step of shifting and
masking of the Verilog "vreg" data structure.
Virtual regions
User-defined design hierarchy regions may be defined and attached to any
existing design region or to the virtuals context tree. They may be used to
reconstruct the RTL hierarchy in a gate-level design, and used to locate virtual
signals. Thus, virtual signals and virtual regions may be used in a gate-level design
to allow the RTL test bench with the gate-level design.
Virtual regions are created and attached using the virtual region command (see
below).