ModelSim XE User’s Manual Version 5.
ModelSim XE is produced by Model Technology Incorporated. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of Model Technology. The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology. The program described in this manual is furnished under a license agreement and may not be used or copied except in accordance with the terms of the agreement.
Software License Agreement IMPORTANT – USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal “Agreement” concerning the use of Software between you, the end user, either individually or as an authorized representative of the company purchasing the license, and Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Mentor Graphics (Singapore) Private Limited, and their majority-owned subsidiaries (“Mentor Graph
Mentor Graphics’ real-time operating systems or other ESD Software, except those explicitly granted in this section, into your products without first signing a separate agreement with Mentor Graphics for such purpose. 3. BETA CODE. 3.1 Portions or all of certain Software may contain code for experimental testing and evaluation (“Beta Code”), which may not be used without Mentor Graphics’ explicit authorization.
Mentor Graphics’ prior written consent. The provisions of this section shall survive the termination or expiration of this Agreement. 5. LIMITED WARRANTY. 5.1 Mentor Graphics warrants that during the warranty period Software, when properly installed, will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free.
CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY. YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE, OR LIABILITY, INCLUDING ATTORNEYS’ FEES, ARISING OUT OF OR IN CONNECTION WITH SUCH USE. 8. INFRINGEMENT. 8.
deletion and destruction of Software, including all copies, to Mentor Graphics’ reasonable satisfaction. 10. EXPORT. Software is subject to regulation by local laws and United States government agencies, which prohibit export or diversion of certain products, information about the products, and direct products of the products to certain countries and certain persons.
expenses. Rev.
Table of Contents Software License Agreement . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 - Introduction (19) ModelSim editions documented in this manual . . . . . . . . . . . . . . . . . . . . . 19 Standards supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SDF and ModelSim XE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Sections in this document . . . . . . . . .
Project operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Working with a Project . Open a project . . . Compile a project . Simulating a project Modifying a project The project command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compilation . . . . . . . . . . . . . Incremental compilation . . . . . . . Library usage . . . . . . . . . . . Verilog-XL compatible compiler options Verilog-XL ‘uselib compiler directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 . 58 . 60 . 62 . 65 Simulation . . . . . . . . . . . . . . Invoking the simulator .
Virtual signals . Virtual functions Virtual regions Virtual types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 104 104 105 Logfile and virtual commands reference table . . . . . . . . . . . . . . . . . . . . .
Process window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 The Process window menu bar . . . . . . . . . . . . . . . . . . . . . . . . . 145 Signals window . . . . . . . . . . . . . . . . . . . . The Signals window menu bar . . . . . . . . . . . . Selecting HDL item types to view . . . . . . . . . . . Forcing signal and net values . . . . . . . . . . . . . Adding HDL items to the Wave and List windows or a logfile Finding HDL items in the Signals window . . . . . . .
VHDL settings page . . . . . Verilog settings page . . . . . SDF settings page . . . . . . Setting default simulation options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 209 211 213 ModelSim Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 - Tcl and ModelSim (241) Tcl features within ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Tcl print references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Tcl online references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Tcl commands . . . . . . . . . . Tcl command syntax . . . . . . if command syntax . . . . . . . set command syntax . . . . . .
[vsim] simulator control variables . . . . . [Project] project file section (MPF files only) Setting variables in INI / MPF files . . . . Variable functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 268 269 269 Preference variables located in TCL files . . . . . . . . . . . . . . . . . . . . . . . 273 User-defined variables . . . . . . . . . . . . . . .
1 - Introduction Chapter contents Standards supported . . . . . . . . . . . . . . . . . . . 18 Assumptions . . . . . . . . . . . . . . . . . . . 18 Sections in this document . . . . . . . . . . . . . . . . . 19 Text conventions. . . . . . . . . . . . . . . . . . . 20 What is an "HDL item" . . . . . . . . . . . . . . . . . . 21 . . .
Standards supported Standards supported ModelSim VHDL supports both the IEEE 1076-1987 and 1076-1993 VHDL, 1164-1993 Standard Multivalue Logic System for VHDL Interoperability, and the 1076.2-1996 Standard VHDL Mathematical Packages standards. Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with either IEEE Standard 1076-1987 or 1076-1993.
Sections in this document The ModeSim Tutorial is available from the ModelSim Help menu. Sections in this document In addition to this introduction, you will find the following major sections in this document: 2 - Design Libraries (2-23) To simulate an HDL design using ModelSim, you need to know how to create, compile, maintain, and delete design libraries as described in this chapter.
Command reference 10 - Tcl and ModelSim (10-239) This chapter provides an overview of Tcl (tool command language) as used with ModelSim. Additional Tcl and Tk (Tcl’s toolkit) can be found through several Tcl online references (10-240). A - ModelSim Variables (A-253) This appendix environment, system and preference variables used in ModelSim. B - ModelSim Shortcuts (B-285) A collection of ModelSim keyboard and mouse shortcuts.
What is an "HDL item" What is an "HDL item" Because ModelSim works with both VHDL and Verilog, “HDL” refers to either VHDL or Verilog when a specific language reference is not needed.
1-22 Introduction ModelSim Xilinx User’s Manual
2 - Design Libraries Chapter contents Design library contents . . Design unit information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 . 24 Design library types . . . . . . . . . . . . . . . . . 24 Library management commands. . . . . . . . . . . . . . . . 25 Working with design libraries . . . . . Creating a library . . . . . . . Viewing and deleting library contents . . Assigning a logical name to a design library Moving a library . .
Design library contents Design library contents A design library is a directory that serves as a repository for compiled design units. The design units contained in a design library consist of VHDL entities, packages, architectures, configurations, and Verilog modules and UDPs (user defined primitives). The design units are classed as follows: • Primary design units Consists of entities, package declarations, configuration declarations, modules, and UDPs.
Library management commands Library management commands These library management commands are available from the Transcript window command line, or from the ModelSim graphic interface. Only brief descriptions are provided here; for more information and command syntax see "ModelSim Commands" (CR-11). Command Description vdel (CR-111) deletes a design unit from a specified library vlib (CR-140) selectively lists the contents of a library.
Working with design libraries Creating a working library with the graphic interface To create a new library with the ModelSim graphic interface, use the Transcriptwindow menu selection: Design > Create a New Library. This brings up a dialog box that allows you to specify the library name along with several mapping options. The Create a New Library dialog box includes these options: Create • a new library and a logical mapping to it Type the new library name into the Library field.
Working with design libraries • Maps to Type or Browse for a mapping for the specified library. This field can be changed only when the create a map to an existing library option is selected. When you click OK, ModelSim creates the specified library directory and writes a specially-formatted file named _info into that directory. The _info file must remain in the directory to distinguish it as a ModelSim library. If a mapping option is selected, a map entry is written to the modelsim.
Working with design libraries Viewing and deleting library contents with the graphic interface Selecting Design > View Library Contents… allows you to view the design units (configurations, modules, packages, entities, and architectures) in the current library and delete selected design units. The Library Contents dialog box includes these options: • Library Select the library you wish to view from the drop-down list.
Working with design libraries You can also delete an architecture without deleting its associated entity. Just select the desired architecture name and click Delete. You are prompted for confirmation before any design unit is actually deleted. Assigning a logical name to a design library VHDL uses logical library names that can be mapped to ModelSim library directories.
Working with design libraries The Library Browser dialog box includes these options: • Show Choose the mapping and library scope to view from the drop-down list. • Library/Type list To view the contents of a library Select the library, then click the View button. This brings up the Library Contents (2-27) dialog box. From there you can also delete design units from the library. To create a new library mapping Click the Add button.
Working with design libraries When you use vmap (CR-147) this way you are modifying the modelsim.ini file. You can also modify modelsim.ini manually by adding a mapping line. To do this, edit the modelsim.ini file using any text editor and add a line under the [Library] section heading using the syntax: = More than one logical name can be mapped to a single directory. For example, suppose the modelsim.
Specifying the resource libraries Specifying the resource libraries VHDL resource libraries Within a VHDL source file, you can use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit. The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit. It does not extend to the next design unit in the file.
Specifying the resource libraries Alternate IEEE libraries supplied The installation directory may contain two or more versions of the IEEE library: • ieeepure Contains only IEEE approved std_logic_1164 packages (accelerated for VSIM). • ieee Contains precompiled Synopsys and IEEE arithmetic packages for the std_logic base type, which have been accelerated by Model Technology. You can select which library to use by changing the mapping in the modelsim.ini file. The modelsim.
2-34 Design Libraries ModelSim Xilinx User’s Manual
3 - Projects and system initialization Chapter contents What is a project? . . . . . . . . . . . . . . . . . . . 36 A new file extension . . . . . . . . . . . . . . . . . . . 36 INI and MPF file comparison . . . . . . . . . . . . . . . . 36 The [Project] section in the .mpf file . . . . . . . . . . . . . . 37 Project operations . . . . . . . . . . . . . . . . . . . 37 Creating a Project . . . . . . . . . .
What is a project? What is a project? A project is a collection entity for an HDL design under specification or test. At a minimum, it has a root directory, a work library and session state which is stored in a .mpf file located in the project’s root directory. A project may also consist of: • HDL source files • subdirectories • Local libraries • References to global libraries A new file extension Why create a new file extension instead of using the .ini extension? Project files with the new .
The [Project] section in the .mpf file • A .mpf project file may be updated with current tool settings, whereas a .ini file is used for initial tool defaults. A .mpf project file also maintains changes to project settings. The [Project] section in the .mpf file Sections within the .ini and .mpf files contain variable settings for libraries, the simulator, and compilers. The .mpf file includes an additional [Project] section located at the bottom of the file that contains one or more variables.
Creating a Project 1 To get started fast, select the Create a Project button from the Welcome to ModelSim screen that opens the first time you start ModelSim 5.3. If this screen is not available, you can enable it by selecting Help > Enable Welcome from the Main window. Clicking the Create a Project button opens the Create a New Project dialog box and a project creation wizard.
Creating a Project Note: The Probe Options button allows you to probe the options within the Create a New Project dialog box. The Create Project Wizard displays option information as the cursor moves over each feature. The Create a New Project dialog box can also be accessed by selecting File > New > New Project from the ModelSim Main window. In the Create a New Project dialog box, you can elect to create a new project from scratch or copy an existing project.
Creating a Project Note: A project’s MPF file is always located in the project’s directory. Once you have specified enough information for the project creation, the OK button is selectable. Select OK to create the project directory with a default work library, and open the project for use. If you created the project from the "Welcome to ModelSim" dialog box, the project wizard now prompts you to enter an HDL source file.
Working with a Project Working with a Project Open a project First, you must have a project open to work with it. To open a project select File > Open > Open Project from the Main window (cd’ing into projects directory won’t work). Once you have opened a project you can create HDL source files by selecting File > New > New Source from the Main window. When you create HDL files in the project’s root directory you are prompted to add them to the project.
Working with a Project 3 Project design simulation settings describe how a specific design unit is loaded and simulated. The simulation settings are edited from the Design > Load New Design pull down menu or by clicking the Load Design icon. 4 Project simulation settings describe simulation specific behavior. These settings are edited from the Options > Simulation pull down menu. Project setting changes take place at different times.
4 - VHDL Simulation Chapter contents Compiling VHDL designs . . Creating a design library . Invoking the VHDL compiler Dependency checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 . 44 . 44 . 45 Simulating VHDL designs . . . . . . . Invoking the simulator from the Main window. . . . . . . . . . . . . . . . . . . . 45 . 45 Using the TextIO package . . . . . . . . . . Syntax for file declaration . . . .
Compiling VHDL designs Compiling and simulating with the GUI Many of the examples in this chapter are shown from the command line. For compiling and simulation within ModelSim’s GUI see: • Compiling with the graphic interface (7-195) • Simulating with the graphic interface (7-202) ModelSim variables Several variables are available to control simulation, provide simulator state feedback, or modify the appearance of the ModelSim GUI.
Simulating VHDL designs VHDL version separately. The vcom (CR-106) command compiles units written with version 1076 -1987 by default; use the -93 option with vcom (CR-106) to compile units written with version 1076 -1993. You can also change the default by modifying the modelsim.ini file (see Chapter 3 - Projects and system initialization for more information). Dependency checking Dependent design units must be reanalyzed when the design units they depend on are changed in the library.
Simulating VHDL designs Selecting the time resolution The simulation time resolution is 1 ns by default. You can select a specific time resolution with the vsim (CR-148) -t option or from the Load Design dialog box. Available resolutions are: 1x, 10x or 100x of fs, ps, ns, us, ms, or sec. For example, to run in picosecond resolution, or 10ps resolution respectively: vsim -t ps topmod vsim -t 10ps topmod The default time resolution can also be changed by modifying the resolution (A283) in the modelsim.
Using the TextIO package Using the TextIO package To access the routines in TextIO, include the following statement in your VHDL source code: USE std.textio.all; A simple example using the package TextIO is: USE std.textio.
TextIO implementation issues Using STD_INPUT and STD_OUTPUT within ModelSim The standard VHDL’87 TextIO package contains the following file declarations: file file input: TEXT is in "STD_INPUT"; output: TEXT is out "STD_OUTPUT"; The standard VHDL’93 TextIO package contains these file declarations: file file input: TEXT open read_mode is "STD_INPUT"; output: TEXT open write_mode is "STD_OUTPUT"; STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard,
TextIO implementation issues This call is even more ambiguous, because the compiler could not determine, even if allowed to, whether the argument "010101" should be interpreted as a string or a bit vector.
TextIO implementation issues The ENDLINE function The ENDLINE function described in the IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1987 contains invalid VHDL syntax and cannot be implemented in VHDL. This is because access types must be passed as variables, but functions only allow constant parameters. Based on an ISAC-VASG recommendation the ENDLINE function has been removed from the TextIO package.
Obtaining the VITAL specification and source code Obtaining the VITAL specification and source code VITAL ASIC Modeling Specification The IEEE 1076.4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers, Inc.: IEEE Customer Service Hoes Lane Tiscataway, NJ 08855-1331 Tel: (800)678-4333 ((908)562-5420 from outside the U.S.) Fax: (908)981-9667 home page: http://www.ieee.
Compiling and Simulating with accelerated VITAL packages VITAL compliance checking If you are using VITAL 2.2b, you must turn off the compliance checking either by not setting the attributes, or by invoking vcom (CR-106) with the option -novitalcheck. Compiling and Simulating with accelerated VITAL packages vcom (CR-106) automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built-in routines.
5 - Verilog Simulation Chapter contents Compilation . . . . . . . . . Incremental compilation . . . . Library usage . . . . . . . Verilog-XL compatible compiler options Verilog-XL ‘uselib compiler directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 . 56 . 58 . 60 . 63 Simulation . . . . . . . . . Invoking the simulator . . . . . Simulation resolution limit . . . . Event order issues . . . . . .
This chapter describes how to compile and simulate Verilog designs with ModelSim Verilog. ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364-1995, and it is recommended that you obtain this specification as a reference manual. In addition to the functionality described in the IEEE Std 1364-1995, ModelSim Verilog includes the following features: • Standard Delay Format (SDF) annotator compatible with many ASIC and FPGA vendor's Verilog libraries.
Compilation Compilation Before you can simulate a Verilog design, you must first create a library and compile the Verilog source code into that library. This section provides detailed information on compiling Verilog designs. For information on creating a design library, see Chapter 2 - Design Libraries.
Compilation In this example, the simulator was run without the graphic interface by specifying the -c option. After the design was loaded, the simulator command run -all was entered, meaning to simulate until there are no more simulator events. Finally, the quit command was entered to exit the simulator. By default, a log of the simulation is written to the file "transcript" in the current directory.
Compilation Compile the design in top down order (assumes work library already exists): % vlog top.v -- Compiling module top Top level modules: top % vlog and2.v -- Compiling module and2 Top level modules: and2 % vlog or2.v -- Compiling module or2 Top level modules: or2 Note that the compiler lists each module as a top level module, although, ultimately, only "top" is a top level module.
Compilation The following is an example of how to compile a design with automatic incremental compilation: % vlog -incr -- Compiling -- Compiling -- Compiling top.v and2.v or2.v module top module and2 module or2 Top level modules: top Now, suppose that you modify the functionality of the "or2" module: % vlog -incr top.v and2.v or2.
Compilation Top level modules: and2 or2 % vlog top.v -- Compiling module top Top level modules: top Note that the first compilation uses the -work asiclib option to instruct the compiler to place the results in the asiclib library rather than the default work library. Since instantiation bindings are not determined at compile time, you must instruct the simulator to search your libraries when loading the design.
Compilation Verilog-XL compatible compiler options See vlog (CR-141) for a complete list of compiler options. The options described here are equivalent to Verilog-XL options. Many of these are provided to ease the porting of a design to ModelSim Verilog. +define+[=] This option allows you to define a macro from the command line that is equivalent to the following compiler directive: ‘define Multiple +define options are allowed on the command line.
Compilation +mindelays This option selects minimum delays from the "min:typ:max" expressions. If preferred, you may defer delay selection until simulation time by specifying the same option on the simulator. +typdelays This option selects typical delays from the "min:typ:max" expressions. If preferred, you may defer delay selection until simulation time by specifying the same option on the simulator. +maxdelays This option selects maximum delays from the "min:typ:max" expressions.
Compilation +libext+ This option works in conjunction with the -y option. It specifies file extensions for the files in a source library directory. By default the compiler searches for files without extensions. If you specify the +libext option, then the compiler will search for a file with the suffix appended to an unresolved name. You may specify only one +libext option, but it may contain multiple suffixes separated by "+".
Compilation Verilog-XL ‘ uselib compiler directive The ‘uselib compiler directive is an alternative source library management scheme to the -v, -y, and +libext compiler options. It has the advantage that a design may reference different modules having the same name. The ‘uselib compiler directive is not defined in the IEEE Std 1364-1995, but ModelSim supports it for compatibility with Verilog-XL. The syntax for the ‘uselib directive is: ‘uselib ...
Compilation ModelSim Verilog supports the ‘uselib directive in a different manner than Verilog-XL. The library files referenced by the ‘uselib directive are not automatically compiled by ModelSim Verilog. The reason for this is that an object library is not allowed to contain multiple modules having the same name, and the results of a single invocation of the compiler can be placed in only one object library.
Simulation Simulation The ModelSim simulator can load and simulate both Verilog and VHDL designs, providing a uniform graphic interface and simulation control commands for debugging and analyzing your designs. The graphic interface and simulator commands are described elsewhere in this manual, while this section focuses specifically on Verilog simulation. Invoking the simulator A Verilog design is ready for simulation after it has been compiled into one or more libraries.
Simulation The time precision should not be unnecessarily small because it will limit the maximum simulation time limit, and it will degrade performance in some cases. If the design contains no ‘timescale directives, then the resolution limit defaults to the "resolution" value specified in the modelsim.ini file (default is 1 ns). In any case, you may override the default resolution limit by specifying the -t option on the command line.
Simulation Tracking down event order dependencies is a tedious task, so ModelSim Verilog aids you with a couple of compiler options: -compat This option turns off optimizations that result in different event ordering than Verilog-XL. ModelSim Verilog generally duplicates Verilog-XL event ordering, but there are caseswhere it is inefficient to do so. Using this option does not help you find the event order dependencies, but it allows you to ignore them.
Simulation • A WRITE/READ or READ/WRITE hazard is flagged even if the write does not modify the variable's value. • Glitches on nets caused by non-guaranteed event ordering are not detected. Verilog-XL compatible simulator options See vsim (CR-148) for a complete list of simulator options. The options described here are equivalent to Verilog-XL options. Many of these are provided to ease the porting of a design to ModelSim Verilog. +alt_path_delays Specify path delays operate in inertial mode by default.
Simulation +no_pulse_msg This option disables the warning message for specify path pulse errors. A path pulse error occurs when a pulse propagated through a path delay falls between the pulse rejection limit and pulse error limits set with the +pulse_r and +pulse_e options. A path pulse error results in a warning message, and the pulse is propagated as an X. The +no_pulse_msg option disables the warning message, but the X is still propagated.
Simulation +pulse_r/ This option controls how pulses are propagated through specify path delays, where is a number between 0 and 100 that specifies the rejection limit as a percentage of the path delay. A pulse less than the rejection limit is suppressed from propagating to the output. If the error limit is not specified (see +pulse_e (569)), then it defaults to the rejection limit.
Cell Libraries Cell Libraries Model Technology is the first Verilog simulation vendor to pass the ASIC Council’s Verilog test suite and achieve the "Library Tested and Approved" designation from Si2 Labs. This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support. As a consequence, many ASIC and FPGA vendors’ Verilog cell libraries are compatible with ModelSim Verilog.
System Tasks distributed delays to work properly. Even so, these delays are usually small enough that the path delays take priority over the distributed delays. The rule is that if a module contains both path delays and distributed delays, then the larger of the two delays for each path shall be used (as defined by the IEEE Std 13641995). This is the default behavior, but you can specify alternate delay modes with compiler directives and options. These options and directives are compatible with Verilog-XL.
System Tasks IEEE Std 1364-1995 system tasks The following system tasks are described in detail in the IEEE Std 1364-1995.
System Tasks Display tasks File I/O tasks PLA modeling tasks $monitorh $fmonitorb $async$or$plane $monitoro $fmonitorh $async$nor$plane $monitoroff $fmonitoro $sync$and$array $monitoron $fopen $sync$nand$array $strobe $fstrobe $sync$or$array $strobeb $fstrobeb $sync$nor$array $strobeh $fstrobeh $sync$and$plane $strobeo $fstrobeo $sync$nand$plane $write $fwrite $sync$or$plane $writeb $fwriteb $sync$nor$plane $writeh $fwriteh $writeo $fwriteo $readmemb $readmemh Timing ch
System Tasks Verilog-XL compatible system tasks The following system tasks are provided for compatibility with Verilog-XL. Although they are not part of the IEEE standard, they are described in an annex of the IEEE Std 1364-1995. $countdrivers $getpattern $sreadmemb $sreadmemh The following system tasks are also provided for compatibility withVerilog-XL, but they are not described in the IEEE Std 1364-1995.
System Tasks The tstamp_cond argument conditions the data_event for the setup check and the clk_event for the hold check. This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments. The tcheck_cond argument conditions the data_event for the hold check and the clk_event for the setup check. This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments.
System Tasks The following system tasks are Verilog-XL system tasks that are not implemented in ModelSim Verilog, but have equivalent simulator commands. $input("filename") This system task read command test from the specified filename. The equivalent simulator command is do . $list[(hierarchical_name)] This system task lists the source code for the specified scope. The equivalent functionality is provided by selecting a module in the graphic interface Structure window.
Compiler Directives Compiler Directives ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364-1995 and some additional Verilog-XL compiler directives for compatibility. Many of the compiler directives (such as ‘define and ‘timescale) take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a ‘resetall directive.
Compiler Directives ‘unconnected_drive ‘undef Verilog-XL compatible compiler directives The following compiler directives are provided for compatibility with VerilogXL. ‘delay_mode_distributed This directive disables path delays in favor of distributed delays. See Delay modes (5-71) for details. ‘delay_mode_path This directive sets distributed delays to zero in favor of path delays. See Delay modes (5-71) for details.
Using the Verilog PLI ‘protect ‘remove_gatenames ‘remove_netnames ‘suppress_faults The following Verilog-XL compiler directives produce warning messages in ModelSim Verilog. These are not implemented in ModelSim Verilog, and any code containing these directives may behave differently in ModelSim Verilog than in Verilog-XL.
Using the Verilog PLI p_tffn checktf; p_tffn sizetf; p_tffn calltf; p_tffn misctf; char *tfname;/* name /* /* /* /* of argument checking callback function */ function return size callback function */ task or function call callback function */ miscellaneous reason callback function */ system task or function */ /* The following fields are ignored by ModelSim Verilog */ int forwref; char *tfveritool; char *tferrmessage; int hash; struct t_tfcell *left_p; struct t_tfcell *right_p; char *namecell_p; int war
Using the Verilog PLI {0} /* last entry must be 0 */ }; Alternatively, you can add an init_usertfs function to explicitly register each entry from the array: void init_usertfs() { p_tfcell usertf = veriusertfs; while (usertf->type) mti_RegisterUserTF(usertf++); } It is an error if the PLI application does not contain a veriusertfs array or an init_usertfs function.
Using the Verilog PLI PLI Application Requirements PLI applications are dynamically loaded into VSIM. A PLI application can consist of one or more dynamically loadable objects. Each of these objects must contain an entry point named init_usertfs( ) and a local veriusertfs table of user tasks and functions. There must be an entry in the table for each function in the object file that can be called externally.
Using the Verilog PLI See also Appendix A - ModelSim Variables for more information on the modelsim.ini file. PLI Example The following example is a trivial, but complete PLI application. hello.c: #include "veriuser.h" static hello() { io_printf("Hi there\n"); } s_tfcell veriusertfs[] = { {usertask, 0, 0, 0, hello, 0, "$hello"}, {0} /* last entry must be 0 */ }; hello.
Using the Verilog PLI The callback reason argument The second argument to a callback function is the reason argument. The values of the various reason constants are defined in the veriuser.h include file. See Section 17 of the IEEE Std 1364 for a description of the reason constants. The following details relate to ModelSim Verilog, and may not be obvious in the IEEE Std 1364.
Using the Verilog PLI reason_interactive For the execution of the $stop system task or any other time the simulation is interrupted and waiting for user input. reason_scope For the execution of the environment command or selecting a scope in the structure window. Also for the call to acc_set_interactive_scope if the callback_flag argument is non-zero. reason_paramvc For the change of value on the system task or function argument. reason_synch For the end of time step event scheduled by tf_synchronize.
Using the Verilog PLI • The sizetf function should return 0 if the system function return value is of Verilog type "real". • The sizetf function should return -32 if the system function return value is of Verilog type "integer". Object handles Many of the object handles returned by the ACC PLI routines are pointers to objects that naturally exist in the simulation data structures, and the handles to these objects are valid throughout the simulation, even after the acc_close routine is called.
Using the Verilog PLI % cc -c -I/modeltech/include veriuser.c % ld -G -o app.sl veriuser.o libapp.a That’s all there is to it. The PLI application is ready to be run with ModelSim Verilog. All that’s left is to specify the resulting object file to the simulator for loading using the Veriuser modesim.ini file entry, the -pli simulator option, or the PLIOBS environment variable (see "Registering PLI applications").
Using the Verilog PLI Type Fulltype Description accBlock accBlock block statement accForLoop accForLoop for loop statement accForeign accShadow foreign scope created by mti_CreateRegion( ) accGenerate accGenerate generate statement accPackage accPackage package declaration accSignal accSignal signal declaration The type and fulltype constants for VHDL objects are defined in the acc_vhdl.h include file.
Using the Verilog PLI acc_fetch_itfarg acc_fetch_tfarg_int acc_fetch_itfarg_int acc_fetch_tfarg_str acc_fetch_itfarg_str acc_fetch_timescale_info acc_fetch_type acc_fetch_type_str acc_fetch_value acc_free acc_handle_by_name acc_handle_calling_mod_m acc_handle_condition acc_handle_conn acc_handle_hiconn acc_handle_interactive_scope acc_handle_loconn acc_handle_modpath acc_handle_notifier acc_handle_object acc_handle_parent acc_handle_path acc_handle_pathin acc_handle_pathout acc_hand
Using the Verilog PLI IEEE Std 1364 TF routines ModelSim Verilog supports the following TF routines, described in detail in the IEEE Std 1364.
Using the Verilog PLI tf_real_to_long tf_rosynchronize tf_irosynchronize tf_scale_longdelay tf_scale_realdelay tf_setdelay tf_isetdelay tf_setlongdelay tf_isetlongdelay tf_setrealdelay tf_isetrealdelay tf_setworkarea tf_isetworkarea tf_sizep tf_isizep tf_spname tf_ispname tf_strdelputp tf_istrdelputp tf_strgetp tf_istrgetp tf_strgettime tf_strlongdelputp tf_istrlongdelputp tf_strrealdelputp tf_istrrealdelputp tf_subtract_long tf_synchronize tf_isynchronize tf_testpvc_flag tf_i
Using the Verilog PLI This routine gets the current simulation time as a 64-bit integer. The low-order bits are returned by the routine, while the high-order bits are stored in the aof_hightime argument. PLI tracing The foreign interface tracing feature is available for tracing user foreign language calls made to the MTI Verilog PLI.
Using the Verilog PLI Arguments Specifies one of the following actions: Value Action Result 1 create log only writes a local file called "mti_trace_" 2 create replay only writes local files called "mti_data_.c", "mti_init_.c", "mti_replay_.c" and "mti_top_.c" 3 create both log and replay -tag Used to give distinct file names for multiple traces. Optional. Examples vsim -trace_foreign 1 mydesign Creates a logfile.
6 - Multiple logfiles, datasets and virtuals Chapter contents Multiple logfiles and datasets . . . . . Opening and viewing datasets . . . . Using datasets with ModelSim commands . Restricting the dataset prefix display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 . 96 . 98 . 99 Virtual Objects (User-defined buses, and more) Virtual signals . . . . . . . . Virtual functions . . . . . . . Virtual regions . . . . . . . . Virtual types . . . . . . . . . .
Multiple logfiles and datasets In the illustration above, the Wave window is split into two panes. The top pane shows the dataset of the current simulation. (The default dataset prefix is "sim".) The bottom pane shows a dataset in the view mode only. (The default dataset prefix is "view".) The sim-mode dataset is located in the active pane, as indicated by the white bar in the left margin. New panes are created with the Wave > File > New Window Pane menu selection.
Multiple logfiles and datasets Once you have specified the logfile and dataset name, the dataset is ready for viewing. To view the dataset, use the Main > View > Dataset menu selection to open the Dataset Browser Select Open to browse for a dataset (this opens the View Dataset dialog box as well). Once the dataset is open, you can select it and choose Make Active to prepare it for viewing. Add signals to the Wave window with add wave command (CR-23).
Multiple logfiles and datasets Virtuals ModelSim supports an additional, subterranean, dataset named "virtuals", which contains references to user-defined buses and other virtual objects (see below). Normally, you will not need to directly reference the virtuals dataset. Using datasets with ModelSim commands Multiple logfiles may be opened when the simulator is invoked by specifying more than one vsim -view option.
Multiple logfiles and datasets Additionally, a Structure or Signals window may be created sensitive to a specified dataset using the -env switch to the view command. For example, view -new signals -env view1 will create a new Signals window sensitive to the view1 dataset. ModelSim remembers a "current context" within each open dataset. You can toggle between the current context of each dataset using the environment command specifying the dataset without a path.
Virtual Objects (User-defined buses, and more) Virtual Objects (User-defined buses, and more) Virtual objects are signal-like or region-like objects created in the GUI that do not exist in the ModelSim simulation kernel. ModelSim release 5.
Virtual Objects (User-defined buses, and more) Virtual signals Virtual signals are aliases for combinations or subelements of signals written to the logfile by the simulation kernel. They may be displayed in the Signals, List or Wave window, accessed by the examine command, and set using the force command. Virtual signals may be created by menu selections in the Signals, Wave or List windows, or with the virtual signal command described below.
Virtual Objects (User-defined buses, and more) whose definition is stored in a special location, and is not visible in the Signals window or to the normal virtual commands. All other virtual signals are considered "explicit virtuals". Virtual functions Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel. They consist of logical operations on logged signals and may be dependent on simulation time.
Logfile and virtual commands reference table Virtual types User-defined enumerated types may be defined in order to display signal bit sequences as meaningful alphanumeric names. The virtual type is then used in a type conversion expression to convert a signal to values of the new type. When the converted signal is displayed in any of the windows, the value will be displayed as the enumeration string corresponding to the value of the original signal.
Logfile and virtual commands reference table Command name Action virtual nolog (CR-130) causes the specified virtual signals to be un-logged by the kernel virtual region (CR-132) creates a new user-defined design hierarchy region virtual save (CR-133) saves the definitions of virtuals to a file virtual show (CR-134) lists the full path names of all the virtuals explicitly defined virtual signal (CR-135) creates a new signal that consists of concatenations of signals and subelements virtual type
7 - ModelSim XE Graphic Interface Chapter contents Window overview . . . . . . . . . . . . . . . . . . 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window overview Window overview The ModelSim simulation and debugging environment consists of nine windows. A brief description of each window follows: • Main window (7-113) The main window from which all subsequent VSIM windows are available. • Dataflow window (7-124) Lets you trace signals and nets through your design by showing related processes. • List window (7-128) Shows the simulation values of selected VHDL signals, and Verilog nets and register variables in tabular format.
Window features Window features ModelSim’s graphic interface provides many features that add to its usability; features common to many of the windows are described below.
Window features • The transcript window now includes an edit popup menu activated via with the right mouse button. • The middle mouse button will allow you to paste the following into the transcript window: – text currently selected in the transcript window, – a current primary X-Windows selection (may be from another application), or Transcript edit popup – contents of the clipboard. Note: Selecting text in the transcript window makes it the current primary X-Windows selection.
Window features • Drop items into these windows: List and Wave windows Note: Drag and drop works to rearrange items within the List and Wave windows as well. Command history Avoid entering long commands twice; use the down and up keyboard arrows to move through the command history for the current simulation.
Window features Finding names, and locating cursors • Find HDL item names with the Edit > Find menu selection in these windows: List, Process, Signals, Source, Structure, Variables, and Wave windows. You can also: • Locate time markers in the List window with the Markers > Goto menu selection. • Locate time cursors in the Wave window with the Cursor > Goto menu selection.
Window features Tree window hierarchical view ModelSim provides a hierarchical, or "tree view" of some aspect of your design in the Structure, Signals, Variables, and Wave windows.
Window features Viewing the hierarchy Whenever you see a tree view, as in the Structure window displayed here, you can use the mouse to collapse or expand the hierarchy. Select the symbols as shown below to change the view of the structure.
Main window Main window The Main window is pictured below as it appears when VSIM is first invoked. Note that your operating system graphic interface provides the windowmanagement frame only; ModelSim handles all internal-window features including menus, buttons, and scroll bars. The menu bar at the top of the window provides access to a wide variety of simulation commands and ModelSim preferences.
Main window The Main window menu bar The menu bar at the top of the Main window lets you access many ModelSim commands and features. The menus are listed below with brief descriptions of the command’s use.
Main window Options (all options are set for the current session only) Transcript File: sets a transcript file to save for this session only Command History: file for saving command history only, no comments Save File: sets filename for Save Main, and Save Main as Saved Lines: limits the number of lines saved in the transcript (default is all) Line Prefix: specify the comment prefix for the transcript Update Rate: specify the update frequency for the Main status bar ModelSim Prompt: change the title of th
Main window View menu All open all VSIM windows Source open and/or view the Source window (7-152) Structure open and/or view the Structure window (7-158) Variables open and/or view the Variables window (7-161) Signals open and/or view the Signals window (7-144) List open and/or view the List window (7-128) Process open and/or view the Process window (7-142) Wave open and/or view the Wave window (7-164) Dataflow open and/or view the Dataflow window (7-124) Datasets opens the Dataset Brows
Main window Macro menu Execute Macro allows you to browse for and execute a DO file (macro) Execute Old PE Macro... calls and executes old PE 4.7 macro without changing the macro to XE 5.3; backslashes may be selected as pathname delimiters Convert Old PE Macro... converts old PE 4.7 macro to XE 5.
Main window lists the currently open windows; select a window name to switch to, or show that window if it is hidden; when the source window is available, the source file name is also indicated; open additional windows from the "View menu" (7-116) in the Main window Help menu About ModelSim display ModelSim application information Release Notes view current release notes with the ModelSim notepad (CR-70) Enable Welcome enables Welcome screen for starting a new project or opening an exi
Main window with the Save Main selection. Since no automatic saves are performed for this file, it is written only when a Save... menu selection is made. The file is written to the current working directory and records the contents of the transcript at the time of the save. Using the saved transcript as a macro (DO file) Saved transcript files can be used as macros (DO files). See the do command (CR43) for more information.
Main window Main window tool bar buttons Button Menu equivalent Command equivalents Copy copy the selected text within the Main window transcript Edit > Copy see: "Mouse and keyboard shortcuts in the Transcript and Source windows" (7-121) Paste paste the copied text to the cursor location Edit > Paste see: "Mouse and keyboard shortcuts in the Transcript and Source windows" (7-121) Restart reloads the design elements and resets the simulation time to zero File > Restart restart Run L
Main window Main window tool bar buttons Button Menu equivalent Command equivalents Step steps the current simulation to the next HDL statement Run > Step…. step Step Over HDL statements are executed but treated as simple statements instead of entered and traced line by line Run > Step Over….
Main window displayed in the Source window and all Notepad windows (enter the notepad command within ModelSim to open the Notepad editor).
Main window Keystrokes Result < control - e >, move insertion cursor to end of line < control - x > cut selection < control - c > < control - v > copy selection insert clipboard The Main window allows insertions or pastes only after the prompt, therefore, you don’t need to set the cursor when copying strings to the command line.
Dataflow window Dataflow window The Dataflow window allows you to trace VHDL signals or Verilog nets through your design. Double-click an item with the left mouse button to move it to the center of the Dataflow display.
Dataflow window The Dataflow window menu bar The following menu commands and button options are available from the Dataflow window menu bar.
Dataflow window Tracing HDL items with the Dataflow window The Dataflow window is linked with the Signals window (7-144) and the Process window (7-142). To examine a particular process in the Dataflow window, click on the process name in the Process window. To examine a particular HDL item in the Dataflow window, click on the item name in the Signals window.
Dataflow window Saving the Dataflow window as a Postscript file Use this Dataflow window menu selection: File > Save Postscript to save the current Dataflow view as a Postscript file. Configure the Postscript output with the following dialog box, or use the Preferences dialog box from this Main window selection: Option > Edit Preferences. The dialog box has the following options: • Postscript File specify the name of the file to save, default is dataflow.
List window List window The List window displays the results of your simulation run in tabular format. The window is divided into two adjustable panes, which allow you to scroll horizontally through the listing on the right, while keeping time and delta visible on the left.
List window The List window menu bar The following menu commands and button options are available from the List window menu bar.
List window Markers menu Add Marker add a time marker at the top of the listing page Delete Marker delete the selected marker from the listing Goto choose the time marker to go to from a list of current markers Prop menu Display Props set display properties for all items in the window: delta settings, trigger on selection, strobe period, and label size Signal Props set label, radix, trigger on/off, and field width for the selected item Window menu Initial Layout restore all windows to the size a
List window Setting List window display properties Before you add items to the List window you can set the window’s display properties. To change when and how a signal is displayed in the List window, make this selection from the List window menu bar: Prop > Display Props. The resulting Modify Display Properties dialog box has the following options. Trigger settings page The Triggers page controls the triggering for the display of new lines in the List window.
List window The Triggers page includes the following options: • Deltas:Expand Deltas When selected with the Trigger on: Signals check box, displays a new line for each time step on which items change, including deltas within a single unit of time resolution. • Deltas:Collapse Deltas Displays only the final value for each time unit in the List window. • Deltas:No Deltas No simulation cycle (delta) column is displayed in the List window. • Trigger On: Signals Triggers on signal changes.
List window Window Properties page The Window Properties page includes these options: • Signal Names Allows you to determine the number of path elements to be shown in the List window. For example, "0" shows the full path. "1" shows only the leaf element. • Max Title Rows The maximum number of rows in the name pane. • Dataset Prefix: Show All Dataset Prefixes Display the dataset prefix associated with each signal pathname. Useful for displaying signals from multiple datasets.
List window Adding HDL items to the List window Before adding items to the List window you may want to set the window display properties (see "Setting List window display properties" (7-131)). You can add items to the List window in several ways. Adding items with drag and drop You can drag and drop items into the List window from the Process, Signals, or Structure window. Select the items in the first window, then drop them into the List window.
List window To use the format (do) file, start with a blank List window, and run the DO file in one of two ways: • use the do (CR-43) command on the command line: do • select File > Load Format from the List window menu bar Use Edit > Select All and Edit > Delete to remove the items from the current List window or create a new, blank List window with the View > New > List selection from the "Main window" (7-113).
List window Signal Properties dialog box allows you to set the item’s label, label width, triggering, and radix. The Modify Signal Properties dialog box includes these options: • Signal Shows the signal you selected with the mouse with its dataset prefix. • Label Allows you to specify the label that is to appear at the top of the List window column for the specified item. • Radix Allows you to specify the radix (base) in which the item value is expressed.
List window • Trigger: Triggers line Specifies that a change in the value of the selected item causes a new line to be displayed in the List window. • Trigger: Does not trigger line Selecting this option in the List Signals window specifies that a change in the value of the selected item does not affect the List window. The trigger specification affects the trigger property of the selected item. See also, "Setting List window display properties" (7-131).
List window Examining simulation results with the List window Because you can use the Main window View menu (7-116) to create a second List window, you can reformat another List window after the simulation run if you decide a different format would reveal the information you’re after. Compare the two illustrations. The divider bar separates resolution and delta from values; signal values are listed in symbolic format; and an item change triggers a new line.
List window Finding items by name in the List window The Find dialog box allows you to search for text strings in the List window. From the List window select Edit > Find to bring up the Find dialog box. Enter an item label and Find it by searching Forward (right) or Reverse (left) through the List window display. The column number of the item found displays at the bottom of the dialog box. Note that you can change an item’s label, see "Setting List window display properties" (7-131).
List window Finding a marker Choose a specific marked line to view with Markers > Goto menu selection.The marker name (on the Goto list) corresponds to the simulation time of the selected line.
List window Key Action searches forward (down) to the next transition on the selected signal searches backward (up) to the previous transition on the selected signal (does not function on HP workstations) opens the find dialog box; find the specified item label within the list display Saving List window data to a file From the List window select Edit > Write List (format) to save the List window data in one of these formats: • tabular writes a text file that looks like
Process window Process window The Process window displays a list of processes (either active or in region) and indicates the pathname of the instance in which the process is located. Each HDL item in the scrollbox is preceded by one of the following indicators: • Indicates that the process is scheduled to be executed within the current delta time. • Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time-out period.
Process window The Process window menu bar The following menu commands and button options are available from the Process window menu bar.
Signals window Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lists the currently open windows; select a window name to switch to, or show that window if it is hidden; when the source window is available, the source file name is also indicated; open additional windows from the "View menu" (7-116) in the Main window, or use the view command (CR-116) Signals window The Signals window is divided into two window panes.
Signals window HDL items you can view One entry is created for each of the following VHDL and Verilog HDL items within the design: VHDL items signals Verilog items nets, register variables, and named events Virtual items (indicated by an orange diamond icon) virtual signals, see "Virtual signals" (6101) for more information The names of any VHDL composite types (arrays and record types) are shown in a hierarchical fashion. Hierarchy also applies to Verilog nets and vector memories.
Signals window The Signals window menu bar The following menu commands are available from the Signals window menu bar.
Signals window View menu Wave/List/Log place the Selected Signals, Signals in Region, or Signals in Design in the Wave window (7-164), List window (7-128), or logfile Filter choose the port and signal types to view (Input Ports, Output Ports, InOut Ports and Internal Signals) in the Signals window Window menu Initial Layout restore all windows to the size and placement of the initial full-screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vert
Signals window when you invoked the simulator. Multiple signals may be selected and forced; the force dialog box remains open until all of the signals are either forced, skipped, or you close the dialog box. See also the force command (CR-56). The Force dialog box includes these options: • Signal Name Specify the signal or net for the applied stimulus. • Value Initially displays the current value, which can be changed by entering a new value into the field.
Signals window • Kind: Drive Attaches a driver to the signal and drives the specified value until the signal or net is forced again or until it is unforced with a noforce command (CR-67). This value is illegal for unresolved VHDL signals. • Kind: Deposit Sets the signal or net to the specified value. The value remains until there is a subsequent driver transaction, or until the signal or net is forced again, or until it is unforced with a noforce command (CR-67).
Signals window Choose one of the following options (ModelSim opens the target window for you): • Selected signal Lists only the item(s) selected in the Signals window. • Signals in region Lists all items in the region that is selected in the Structure window. • Signals in design Lists all items in the design.
Signals window Defining clock signals Selecting Clock from the Edit menu allows you to define clock signals by Name, Period, Duty Cycle, Offset, and whether the first rising edge is rising or falling.
Source window Source window The Source window allows you to view and edit your HDL source code. Select an item in the Structure window (7-158) or use the File menu to add a source file to the window, then select a process in the Process window (7-142) to view that process; an arrow next to the line numbers indicates the selected process. (Your source code can remain hidden if you wish, see "Source code security and nodebug" (C-292). A dot next to a line number indicates a breakpoint.
Source window The Source window menu bar The following menu commands are available from the Source window menu bar. File menu New edit a new (VHDL, Verilog or Other) source file Open select a source file to open Use Source specifies an alternative file to use for the current source file; this alternative source mapping exists for the current simulation only Source Directory add to a list of directories (the SourceDir variable in modelsim.
Source window Object menu Describe displays information about the selected HDL item; same as the describe command (CR-41); the item name is shown in the title bar Examine displays the current value of the selected HDL item; same as the examine (CR-51) command; the item name is shown in the title bar Options menu Options open the Source Options dialog box, see "Setting Source window options" (7-157) Window menu Initial Layout restore all windows to the size and placement of the initial full-screen la
Source window The Source window tool bar er p ov st e st ep d fin y st e pa co p cu t fi l e rc e so u ve sa op en so u rc e fi l e Buttons on the Source window tool bar gives you quick access to these ModelSim commands and functions.
Source window Source window tool bar buttons Button Menu equivalent Other equivalents Paste paste the copied text to the cursor location Edit > Paste see: "Mouse and keyboard shortcuts in the Transcript and Source windows" (7-121) Find find the specified text string within the source file; match case option Edit > Find none Step steps the current simulation to the next HDL statement none use step command at the VSIM prompt Step Over none see: step (CR-93) command use the step -over command at
Source window Setting Source window options Access the Source window options with this Source menu selection: Options > Options.
Structure window Structure window The Structure window provides a hierarchical view of the structure of your design. An entry is created by each HDL item within the design. (Your design structure can remain hidden if you wish, see "Source code security and -nodebug" (C-292).) HDL items you can view The following HDL items for VHDL and Verilog are represented by hierarchy within Structure window.
Structure window Instance name components in the Structure window An instance name displayed in the Structure window consists of the following parts: where: instantiation label (architecture) entity or module • instantiation label Indicates the label assigned to the component or module instance in the instantiation statement. • entity or module Indicates the name of the entity or module that has been instantiated.
Structure window Edit menu Copy copy the current selection in the Structure window Sort sort the structure tree in either ascending, descending, or declaration order Expand Selected expands the hierarchy of the selected item Collapse Selected collapses the hierarchy of the selected item Expand All expands the hierarchy of all items that can be expanded Collapse All collapses the hierarchy of all expanded items Find...
Variables window Variables window The Variables window is divided into two window panes. The left pane lists the names of HDL items within the current process. The right pane lists the current value(s) associated with each name. The pathname of the current process is displayed at the bottom of the window. (The internal variables of your design can remain hidden if you wish, see "Source code security and -nodebug" (C-292).
Variables window The Variables window menu bar The following menu commands are available from the Variables window menu bar.
Variables window Window menu Initial Layout restore all windows to the size and placement of the initial full-screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lists the currently open windows; select a window name to switch to, or show that window if it is hidden; when the source wi
Wave window Wave window The Wave window, like the List window, allows you to view the results of your simulation. In the Wave window, however, you can see the results as HDL waveforms and their values. The Wave window is divided into a number of window panes. unused pane There are two cursor panes, as shown below. The left pane shows the time value for each cursor. The selected cursor’s value is highlighted. The right pane shows the absolute time value for each cursor and relative time between cursors.
Wave window The pathname pane displays signal pathnames. Signals may be displayed with full pathnames, as shown here, or with only the leaf element displayed. The selected signal is highlighted. The white bar along the left margin indicates the selected Waveset (see Wave window panes (7-167)). pathnames pane A values pane displays the values of the displayed signals. Signal values may be displayed in analog step, analog interpolated, analog backstep, literal, logic, and event formats.
Wave window waveform pane cursors The waveform pane displays the waveforms that correspond to the displayed signal pathnames. It also displays up to 20 cursors. The window pane below the pathnames window pane and to the left of the cursor panes is unused at this time. All window panes in the Wave window may be resized by clicking and dragging the bar between any two panes. Using Dividers Dividing lines may be placed in the pathname and values window panes by selecting File > New Divider.
Wave window Using dividers Wave window panes The pathnames, values and waveforms window panes of the Wave window display may be split to accommodate signals from one or more datasets. Selecting File > New Window Pane creates a space below the selected waveset and makes the new window pane the selected pane. (The selected wave window pane is indicated by a white bar along the left margin of the pane.
Wave window HDL items you can view VHDL items (indicated by a dark blue square) signals and process variables Verilog items (indicated by a lighter blue circle) nets, register variables, and named events Virtual items (indicated by an orange diamond) virtual signals, buses, and functions, see "Virtual Objects (User-defined buses, and more)" (6-100) for more information 7-168 ModelSim XE Graphic Interface ModelSim Xilinx User’s Manual
Wave window Note: Constants, generics, parameters, and memories are not viewable in the List or Wave windows. The data in the item values windowpane is very similar to the Signals window, except that the values change dynamically whenever a cursor in the waveform windowpane is moved. At the bottom of the waveform windowpane you can see a time line, tick marks, and a readout of each cursor’s position.
Wave window Save Format saves the current Wave window display and signal preferences to a .do (macro) file; running the .do file will reformat the Wave window to match the display as it appeared when the .do file was created Load Format run a Wave window format (.
Wave window Combine combine the selected fields into a user-defined bus Sort sort the top-level items in the name pane; sort with full path name or viewed name; use ascending, descending or declaration order Find...
Wave window Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows lists the currently open windows; select a window name to switch to, or show that window if it is hidden; when the source window is available, the source file name is also indicated; open additional windows from the "View menu" (7-116) in the Main window, or use the view c
Wave window Wave window tool bar buttons Button Menu equivalent Other options Save Wave Format saves the current Wave window display and signal preferences to a do (macro) file File > Save Format none Print Waveform prints a user-selected range of the current Wave window display to a printer or a file File >Print none Cut cut the selected signal within the Wave window Edit > Cut none Copy copy the selected signal in the signalname pane Edit > Copy none Paste paste the copied signal above ano
Wave window Wave window tool bar buttons Button Menu equivalent Other options Find Previous Transition locate the previous signal value change for the selected signal Edit > Find > Reverse Keyboard: Shift + Tab Find Next Transition locate the next signal value change for the selected signal Edit > Find > Forward Keyboard: Tab Zoom in 2x zoom in by a factor of two from the current view Zoom > Zoom In Keyboard: i I or + Zoom out 2x zoom out by a factor of two from current view Zoom > Zoom Out K
Wave window Wave window tool bar buttons Button Menu equivalent Other options Continue Run continue the current simulation run Main menu: Run > Continue see: run (CR-86) Run -All run to current simulation forever, or until it hits a breakpoint or specified break event* Main menu: Run > Run -All see: run (CR-86), also see "Assertion settings page" (7-213) Break stop the current simulation run none none Adding HDL items in the Wave window Before adding items to the Wave window you may want to set
Wave window Adding items with a Wave window format file To use a Wave window format file you must first save a format file for the design you are simulating.
Wave window In the illustration below, four data signals have been combined to form a new bus called DATA1. Notice, the new bus has a value that is made up of the values of its component signals arranged in a specific order. Virtual objects are indicated by an orange diamond. A group is simply a container for any number of signals. It has no value, and the signals contained within it may be arranged in any order.
Wave window Other virtual items in the Wave window See "Virtual Objects (User-defined buses, and more)" (6-100) for information about other virtual item viewable in the Wave window. Editing and formatting HDL items in the Wave window Once you have the HDL items you want in the Wave window, you can edit and format the list in the name/value pane to create the view you find most useful. (See also, "Setting Wave window display properties" (7-182).
Wave window To edit an item: Select the item’s label in the left name/value windowpane or its waveform in the right windowpane. Move, copy or remove the item by selecting commands from the Wave window Edit menu (7-170) menu.
Wave window The Wave Signal Properties dialog box includes these options: • Signal Indicates the name of the currently selected signal. • Label Allows you to specify a new label (in the pathname pane) for the selected item. • Height Allows you to specify the height (in pixels) of the waveform. • Color Lets you override the default color of a waveform by selecting a new color from the color palette, or by entering an X-Windows color name.
Wave window • Format: Analog [Step | Interpolated | Backstep] All signals in this illustration are the same /top/clk signal. Starting with "analog step", the /top/clk signal has been relabeled to illustrate each different wave formats. Analog Step Displays a waveform in step style. Analog Interpolated Displays the waveform in interpolated style. Analog Backstep Displays the waveform in backstep style. Often used for power calculations.
Wave window • Format: Literal Displays the waveform as a box containing the item value (if the value fits the space available). This is the only format that can be used to list a record. • Format: Logic Displays values as 0, 1, X, Z, H, L, U, or -. • Format: Event Marks each transition during the simulation run. Setting Wave window display properties You can define the display properties of the pathname and values window panes by selecting Edit > Display Properties in the Wave window.
Wave window Show All Dataset Prefixes if 2 or more Displays all dataset prefixes if 2 or more datasets are displayed. "sim" is the default prefix for the current simulation. Show No Dataset Prefixes No dataset prefixes will be display. This selection is useful if you are only running a single simulation. • Value Justify Specifies whether the signal values will be justified to the left margin or the right margin in the values window pane.
Wave window interval measurement te d) pr cu e rs fin vi or ou d s ne tra xt ns tra zo iti ns on om iti on in zo 2 om x ou t2 zo x om ar e zo om a fu ll fin d (s el ec te le cu d de ad These Wave window buttons give you quick access to cursor placement and zooming. rs or Using time cursors in the Wave window selected cursor is bold Click and drag with the center mouse button to zoom in on an are of the display. When the Wave window is first drawn, there is one cursor located at time zero.
Wave window selected cursor is drawn as a bold solid line; all other cursors are drawn with thin solid lines. Remove cursors by selecting them and choosing using the Cursor > Delete Cursor menu selection (or the Delete Cursor button shown below). Add Cursor add a cursor to the center of the waveform window Delete Cursor delete the selected cursor from the window Finding a cursor The cursor value (on the Goto list) corresponds to the simulation time of that cursor.
Wave window Zooming - changing the waveform display range Zooming lets you change the simulation range in the windowpane display. You can zoom with either the Zoom menu, toolbar buttons, mouse, keyboard, or VSIM commands. Using the Zoom menu You can use the Wave window menu bar, or call up the Zoom menu by clicking the right mouse button (of a three-button mouse) in the right windowpane. Note: The right mouse button of a two-button mouse will not open the Zoom menu.
Wave window Zooming with the toolbar buttons These zoom buttons are available on the toolbar: Zoom in 2x zoom in by a factor of two from the current view Zoom area use the cursor to outline a zoom area Zoom out 2x zoom out by a factor of two from current view Zoom Full zoom out to view the full range of the simulation from time 0 to the current time Zooming with the mouse To zoom with the mouse, position the mouse cursor to the left side of the desired zoom interval, press the middle mouse button (thre
Wave window Key Action scroll waveform display up scroll waveform display down scroll waveform display left scroll waveform display right scroll waveform display up by page scroll waveform display down by page searches forward (right) to the next transition on the selected signal - finds the next edge searches backward (left) to the previous transition on the selected signal - finds the previous edge
Wave window Saving waveforms Saving a .eps file Use the File > Print Postscript menu selection in the Wave window to save the waveform as a .eps file. Printing and writing preferences are controlled by the dialog box shown below. The Write Postscript dialog box includes these options: Printer • File name enter a filename for the encapsulated Postscript (.eps) file to be created; or browse to a previously created .eps file and use that filename.
Wave window Signal Selection • All signals prints all signals • Current View prints signals in current view • Selected prints all selected signals Time Range • Full Range prints all specified signals in the full simulation range • Current view prints specified signals for the viewable time range • Custom prints the specified signals for user-designated From and To time Setup button See "Printer Page Setup" (7-193) 7-190 ModelSim XE Graphic Interface ModelSim Xilinx User’s Manual
Wave window Printing on Windows platforms Use the File > Print menu selection in the Wave window to print all or part of the waveform in the current Wave window, or save the waveform as a printer file (a Postscript file for Postscript printers). Printing and writing preferences are controlled by the dialog box shown below. Printer • Name Choose the printer from the drop-down menu. Set printer properties with the Properties button. • Status Indicates the availability of the selected printer.
Wave window • Where The printer port for the selected printer. • Comment The printer comment from the printer properties dialog box. • Print to file Make this selection to print the waveform to a file instead of a printer. The printer driver determines what type of file is created. Postscript printers create a Postscript (.ps) file, non-Postscript printers print a .prn or printer control language file. To create an encapsulated Postscript file (.eps) use the File > Print Postscript menu selection.
Wave window Printer Page Setup Clicking the Setup button in the Write Postscript or Print dialog box allows you to define the following options (this is the same dialog that opens with File > Page setup menu selection).
Wave window • Label width specify Auto Adjust to accommodate any length label, or set a fixed label width • Cursors turn printing of cursors on or off • Color select full color printing, grayscale or black and white • Scaling specify a Fixed output time width in nanoseconds per page – the number of pages output is automatically computed; or, select Fit to to define the number of pages to be output based on the paper size and time settings; if set, the timewidth per page is automatically computed • Orientat
Compiling with the graphic interface Compiling with the graphic interface To compile either VHDL or Verilog designs, select the Compile button on the Main window toolbar. The Compile HDL Source Files dialog box opens as shown below.
Compiling with the graphic interface Transcript and Source windows" (7-121) for additional source file editing information. Locating source errors during compilation If a compiler error occurs during compilation, a red error message is printed in the Main transcript. Double-click on the error message to open the source file in an editable Source window with the error highlighted.
Compiling with the graphic interface VHDL compiler options page • Use 1993 language syntax Specifies the use of VHDL93 during compilation. The 1987 standard is the default. Same as the -93 switch for the vcom command (CR-106). Edit the VHDL93 (A-260) in the modelsim.ini to set a permanent default. • Don’t put debugging info in library Models compiled with this option do not use any of the ModelSim debugging features. Consequently, your user will not be able to see into the model.
Compiling with the graphic interface explicit function definition. Same as the -explicit switch for the vcom command (CR-106). Edit the Explicit (A-261) in the modelsim.ini to set a permanent default. Although it is not intuitively obvious, the = operator is overloaded in the std_logic_1164 package. All enumeration data types in VHDL get an “implicit” definition for the = operator. So while there is no explicit = operator, there is an implicit one.
Compiling with the graphic interface • Multiple drivers on unresolved signal Flags any unresolved signals that have multiple drivers. Edit the Show_Warning5 (A-260) in the modelsim.ini to set a permanent default. Check for: • Synthesis Turns on limited synthesis-rule compliance checking. Edit the CheckSynthesis (A-261) in the modelsim.ini to set a permanent default. • Vital Compliance Toggle Vital compliance checking. Edit the NoVitalCheck (A-261) in the modelsim.ini to set a permanent default.
Compiling with the graphic interface Verilog compiler options page • Enable run-time hazard checks Enables the run-time hazard checking code. Same as the -hazards switch for the vlog command (CR-141). Edit the Hazard (A-261) in the modelsim.ini to set a permanent default. • Don’t put debugging info in library Models compiled with this option do not use any of the ModelSim debugging features. Consequently, your user will not be able to see into the model.
Compiling with the graphic interface • Convert Verilog identifiers to upper-case Converts regular Verilog identifiers to uppercase. Allows case insensitivity for module names. Same as the -u switch for the vlog command (CR-141). Edit the UpCase (A-262) in the modelsim.ini to set a permanent default. • Disable loading messages Disables loading messages in the Transcript window. Same as the -quiet switch for the vlog command (CR-141). Edit the Quiet (A-261) in the modelsim.ini to set a permanent default.
Simulating with the graphic interface Simulating with the graphic interface The Load Design dialog box is activated when the Load Design button is selected from the Main window toolbar. Four pages - Design, VHDL, Verilog, and SDF - allow you to select various simulation options. You can switch between pages to modify settings, then begin simulation by selecting the Load button.
Simulating with the graphic interface Design selection page Note: The Exit button closes the Load Design dialog box and quits ModelSim. The Design page includes these options: • Simulator Resolution (-time []) The drop-down menu sets the simulator time units (original default is ns). • Library Specifies a library for viewing in the Design Unit list box.
Simulating with the graphic interface a library name. You can also use the Browse button to locate a library among your directories. Make certain your selection is a valid ModelSim library - it must include an _info file and must have been created from ModelSim’s vlib command (CR-140). Once the library is selected you can view its design units within the Design Unit list box. • Simulate ( | | [()]) Specifies the design unit(s) to simulate.
Simulating with the graphic interface VHDL settings page The VHDL page includes these options: Generics The Add button opens a dialog box that allows you to specify the value of generics within the current simulation; generics are then added to the Generics list. You may also select a generic on the listing to Delete or Edit (opens the dialog box below).
Simulating with the graphic interface From Specify a Generic dialog box you can set the following options. • Generic Name (-g ) The name of the generic parameter. You can make a selection from the drop-down menu or type it in as it appears in the VHDL source (case is ignored).
Simulating with the graphic interface • STD_OUTPUT (-std_output ) Specifies the file to use for the VHDL textio STD_OUTPUT file. Use the Browse button to locate a file within your directories.
Simulating with the graphic interface The Verilog page includes these options: • Delay Selection (+mindelays | +typdelays | +maxdelays) Use the drop-down menu to select timing for min:typ:max expressions. Also see: "Timing check disabling" (4-46). • Additional Search Libraries (-L ) Specifies one or more libraries to search for the design unit(s) you wish to simulate. Type in a library name or use the Browse button to locate a library within your directories.
Simulating with the graphic interface SDF settings page The SDF (Standard Delay Format) page includes these options: SDF Files The Add button opens a dialog box that allows you to specify the SDF files to load for the current simulation; files are then added to the Region/File list. You may also select a file on the listing to Delete or Edit (opens the dialog box below).
Simulating with the graphic interface From the Specify an SDF File dialog box you can set the following options. • SDF file ([] = ) Specifies the SDF file to use for annotation. Use the Browse button to locate a file within your directories. • Apply to region Specifies the design region to use with the selected SDF options. • Delay Selection (-sdfmin | -sdftyp | -sdfmax) Drop-down menu selects delay timing (min, typ or max) to be used from the specified SDF file.
Simulating with the graphic interface Setting default simulation options Use the Options > Simulation... menu selection to bring up the Simulation Options dialog box shown below. Options you may set for the current simulation include: default radix, default force type, default run length, iteration limit, warning suppression, and break on assertion specifications. OK accepts the changes made and closes the dialog box. Apply makes the changes with the dialog box open so you can test your settings.
Simulating with the graphic interface The Default page includes these options: • Default Radix Sets the default radix for the current simulation run. You can also use the radix (CR-81) command to set the same temporary default. A permanent default can be set by editing the DefaultRadix (A-263) in the modelsim.ini file. The chosen radix is used for all commands (force (CR-56), examine (CR-51), change (CR-34) are examples) and for displayed values in the Signals, Variables, Dataflow, List, and Wave windows.
Simulating with the graphic interface Assertion settings page The Assertions page includes these options: • Break on Assertion Selects the assertion severity that will stop simulation. Edit the BreakOnAssertion (A-263) in the modelsim.ini to set a permanent default. • Ignore Assertions For Selects the assertion type to ignore for the current simulation. Multiple selections are possible. Edit the IgnoreFailure, IgnoreError, IgnoreWarning, or IgnoreNote (A-264) variables in the modelsim.
ModelSim Quick Start ModelSim Quick Start The ModelSim Quick Start guide is available by clicking the Quick Start button in the Welcome to ModelSim window or by selecting Help > Quick Start Menu from the Main window. The Quick Start guide includes three examples (select the See an Example button) that shows the process for creating a project, creating a library, compiling source code and simulating the code.
Use the Quick Start guide to find online answers to the following questions: • What is a ModelSim Project? • What is a ModelSim Library? • What is VSIM, VCOM & VLOG? • How can I get started fast? • How do I create a project in ModelSim? • How do I specify design components of a project? • How do I compile my project? • How do I simulate my project? • How do I stop working on a project? • How do I modify a project? • When do project setting changes take effect? • What does enabling auto update of project set
7-216 ModelSim XE Graphic Interface ModelSim Xilinx User’s Manual
8 - Standard Delay Format (SDF) Timing Annotation Chapter contents SDF and ModelSim XE . . . . . . . . . . . . . . . 218 Specifying SDF files for simulation . Instance specification . . . SDF specification with the GUI Errors and warnings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 218 219 219 VHDL VITAL SDF . . . . . SDF to VHDL generic matching Resolving errors. . . . . . . . . . . . . . . . . . . .
Specifying SDF files for simulation SDF and ModelSim XE For ModelSim XE, SDF timing annotation can only be applied to the Xilinx libraries shown below; all other libraries will simulate without annotation. The following mappings are defined in XE’s modelsim.ini file: simprim = $MODEL_TECH/../xilinx/vhdl/simprim logiblox = $MODEL_TECH/../xilinx/vhdl/logiblox unisim = $MODEL_TECH/../xilinx/vhdl/unisim unisim5K = $MODEL_TECH/../xilinx/vhdl/unisim5K simprims_ver = $MODEL_TECH/..
Specifying SDF files for simulation several models, each having its own SDF file. In this case, specify an SDF file for each instance. For example, vsim -sdfmax /system/u1=asic1.sdf -sdfmax /system/u2=asic2.sdf system SDF specification with the GUI As an alternative to the command-line options, you may specify SDF files in the Load Design dialog box under the SDF tab. This dialog box is presented if you invoke the simulator without any arguments or if you select "Load New Design...
VHDL VITAL SDF warnings, or select Reduce SDF errors to warnings (-sdfnoerror) to change errors to warnings. See "Troubleshooting" (8-230) for more information on errors and warnings, and how to avoid them. VHDL VITAL SDF VHDL SDF annotation works on VITAL cells only. The IEEE 1076.4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation.
VHDL VITAL SDF SDF construct Matching VHDL generic name (WIDTH (COND (reset==1’b0) clk) (5)) tpw_clk_reset_eq_0 Resolving errors If the simulator finds the cell instance but not the generic then an error message is issued. For example, ERROR: myasic.sdf(18): Instance ’/testbench/dut/u1’ does not have a generic named ’tpd_a_y’ In this case, make sure that the design is using the appropriate VITAL library cells. If it is, then there is probably a mismatch between the SDF and the VITAL cells.
Verilog SDF vsim -vital2.2b -sdfmax /testbench/u1=myasic.sdf testbench For more information on resolving errors see "Troubleshooting" (8-230). Verilog SDF Verilog designs may be annotated using either the simulator command-line options or the $sdf_annotate system task (also commonly used in other Verilog simulators). The command-line options annotate the design immediately after it is loaded, but before any simulation events take place.
Verilog SDF "tool_control". The "tool_control" argument means to use the delay specified on the command line by +mindelays, +typdelays, or +maxdelays (defaults to +typdelays). "" String that specifies delay scaling factors. Optional. The format is "::". Each multiplier is a real number that is used to scale the corresponding delay in the SDF file. "" String that overrides the delay selection. Optional.
Verilog SDF The IOPATH construct usually annotates path delays. If the module contains no path delays, then all primitives that drive the specified output port are annotated. INTERCONNECT and PORT are matched to input port: SDF Verilog (INTERCONNECT u1.y u2.a (5)) input a; (PORT u2.a (5)) inout a; Both of these constructs identify a module input or inout port and create an internal net that is a delayed version of the port. This is called a Module Input Port Delay (MIPD).
Verilog SDF SETUP is matched to $setup and $setuphold: SDF Verilog (SETUP d (posedge clk) (5)) $setup(d, posedge clk, 0); (SETUP d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0); HOLD is matched to $hold and $setuphold: SDF Verilog (HOLD d (posedge clk) (5)) $hold(posedge clk, d, 0); (HOLD d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0); SETUPHOLD is matched to $setup, $hold, and $setuphold: SDF Verilog (SETUPHOLD d (posedge clk) (5) (5)) $setup(d, posedge clk, 0); (SETUPHOLD d (
Verilog SDF RECREM is matched to $recovery, $removal, and $recrem: SDF Verilog (RECREM (negedge reset) (posedge clk) (5) (5)) $recovery(negedge reset, posedge clk, 0); (RECREM (negedge reset) (posedge clk) (5) (5)) $removal(negedge reset, posedge clk, 0); (RECREM (negedge reset) (posedge clk) (5) (5)) $recrem(negedge reset, posedge clk, 0); SKEW is matched to $skew: SDF Verilog (SKEW (posedge clk1) (posedge clk2) (5)) $skew(posedge clk1, posedge clk2, 0); WIDTH is matched to $width: SDF Verilo
Verilog SDF Optional edge specifications Timing check ports and path delay input ports may have optional edge specifications. The annotator uses the following rules to match edges: • A match occurs if the SDF port does not have an edge. • A match occurs if the specify port does not have an edge. • A match occurs if the SDF port edge is identical to the specify port edge. • A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge.
Verilog SDF Timing check edge specifiers may also use explicit edge transitions instead of posedge and negedge. However, the SDF file is limited to posedge and negedge. The explicit edge specifiers are 01, 0x, 10, 1x, x0, and x1. The set of [01, 0x, x1] is equivalent to posedge, while the set of [10, 1x, x0] is equivalent to negedge. A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port.
SDF for Mixed VHDL and Verilog Designs Rounded timing values The SDF TIMESCALE construct specifies time units of values in the SDF file. The annotator rounds timing values from the SDF file to the time precision of the module that is annotated. For example, if the SDF TIMESCALE is 1ns and a value of .016 is annotated to a path delay in a module having a time precision of 10ps (from the timescale directive), then the path delay receives a value of 20ps. The SDF value of 16ps is rounded to 20ps.
Troubleshooting Troubleshooting Several common mistakes in SDF annotation are outlined below. Specifying the wrong instance By far, the most common mistake in SDF annotation is to specify the wrong instance to the simulator’s SDF options. The most common case is to leave off the instance altogether, which is the same as selecting the top-level design unit.
Troubleshooting Mistaking a component or module name for an instance label Another common error is to specify the component or module name rather than the instance label. For example, the following invocation is wrong for the above testbenches: vsim -sdfmax /testbench/myasic=myasic.sdf testbench This results in the following error message: ERROR: myasic.sdf: The design does not have an instance named ’/testbench/myasic’.
Obtaining the SDF specification Obtaining the SDF specification SDF specification is available from Open Verilog International: Lynn Horobin phone: (408)358-9510 fax: (408)358-3910 email: info@ovi.org home page: http://www.ovi.
9 - Value Change Dump (VCD) Files Chapter contents ModelSim VCD commands and VCD tasks . . . . . . . . . . . 234 A VCD file from source to output . . . . . . . . . . . . . . 234 VHDL source code . . . . . . . . . . . . . . . . . 234 VCD simulator commands . . . . . . . . . . . . . . . 235 VCD output . . . . . . . . . . . . . . . . . . . 235 This chapter explains Model Technology’s Verilog VCD implementation for ModelSim. The VCD file format is specified in the IEEE 1364 standard.
ModelSim VCD commands and VCD tasks ModelSim VCD commands and VCD tasks ModelSim VCD commands map to IEEE 1364 VCD system tasks and appear in the VCD file along with the results of those commands. The table below shows the mapping of the extended VCD commands to the IEEE 1364 keywords.
A VCD file from source to output architecture RTL of SHIFTER_MOD is begin process (CLK,RESET) begin if (RESET = ’1’) then Q <= (others => ’0’) ; elsif (CLK’event and CLK = ’1’) then Q <= Q(Q’left - 1 downto 0) & data_in ; end if ; end process ; end ; VCD simulator commands At simulator time zero, the designer executes the following commands and quits the simulator at time 1200: vcd file output.
A VCD file from source to output VCD output $comment File created using the following command: vcd file output.vcd $date Fri Apr 12 09:07:17 1996 $end $version ModelSim EE/PLUS 5.
A VCD file from source to output 0& 0’ 0( 0) 0* 0+ 1, $end #350 0! #400 1! 1+ #450 0! #500 1! 1* #550 0! #600 1! 1) #650 0! #700 1! 1( #750 0! #800 1! 1’ #850 0! #900 1! 1& #950 0! ModelSim Xilinx User’s Manual #1000 1! 1% #1050 0! #1100 1! 1$ #1150 0! 1" 0$ 0% 0& 0’ 0( 0) 0* 0+ 0, #1200 1! $dumpa ll 1! 1" 1# 0$ 0% 0& 0’ 0( 0) 0* 0+ 0, $end Value Change Dump (VCD) Files 9-237
9-238 Value Change Dump (VCD) Files ModelSim Xilinx User’s Manual
10 - Tcl and ModelSim Chapter contents Tcl features within ModelSim . . . . . . . . . . . . . . . 240 Tcl References . . . . . . . . . . . . . . . 240 Tcl commands . . . . . . . Tcl command syntax . . . . if command syntax . . . . . set command syntax . . . . Command substitution . . . . Command separator. . . . . Multiple-line commands . . . Evaluation order . . . . . Tcl relational expression evaluation Variable substitution . . . . System commands . . . . . . . . . . . .
Tcl features within ModelSim Using Tcl with ModelSim gives you these features: • command history (like that in C shells) • full expression evaluation and support for all C-language operators • a full range of math and trig functions • support of lists and arrays • regular expression pattern matching • procedures • the ability to define your own commands • command substitution (that is, commands may be nested) Tcl References Tcl print references Two sources of information about Tcl are Tcl and the Tk Toolki
Tcl commands Tcl commands The Tcl commands are listed below. For complete information on Tcl commands use the Main window menu selection: Help > Tcl Man Pages, or refer to one of the Tcl/Tk resources noted above. Also see "Preference variables located in TCL files" (A-271) for information on Tcl variables.
Previous ModelSim command if Command changed to (or replaced by) replaced by the Tcl if command, see "if command syntax" for more information (10-245) list add list (CR-19) nolist | nowave delete (CR-40) with either list or wave specified set replaced by the Tcl set command, see "set command syntax" (10-246) for more information source vsource (CR-159) wave add wave (CR-23) Tcl command syntax The former ModelSim commands, if and set are now Tcl commands.
Tcl commands characters and included in the word. Command substitution, variable substitution, and backslash substitution are performed on the characters between the quotes as described below. The double-quotes are not retained as part of the word. 5 If the first character of a word is an open brace ("{") then the word is terminated by the matching close brace ("}").
8 If a backslash ("\") appears within a word then backslash substitution occurs. In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word. This allows characters such as double quotes, close brackets, and dollar signs to be included in words without triggering special processing. The following table lists the backslash sequences that are handled specially, along with the value that replaces each sequence.
Tcl commands 9 If a hash character ("#") appears at a point where Tcl is expecting the first character of the first word of a command, then the hash character and the characters that follow it, up through the next newline, are treated as a comment and ignored. The comment character only has significance when it appears at the beginning of a command. 10 Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command.
set command syntax The Tcl set reads and writes variables. Note that in the syntax below the "?" indicates an optional argument. Syntax set varName ?value? Description Returns the value of variable varName. If value is specified, then set the value of varName to value, creating a new variable if one doesn’t already exist, and return its value.
Tcl commands This feature allows VHDL variables and signals, and Verilog nets and registers to be accessed using: [examine - name] The %name substitution is no longer supported. Everywhere %name could be used, you now can use [examine -value - name] which allows the flexibility of specifying command options. The radix specification is optional. Command separator A semicolon character (;) works as a separator for multiple commands on the same line.
Tcl relational expression evaluation When you are comparing values, the following hints may be useful: • Tcl stores all values as strings, and will convert certain strings to numeric values when appropriate. If you want a literal to be treated as a numeric value, don't quote it. if {[exa var_1] == 345}... The following will also work: if {[exa var_1] == "345"}... • However, if a literal cannot be represented as a number, you must quote it, or Tcl will give you an error.
List processing Environment variables can also be set using the env array: set env(SHELL) /bin/csh See "Simulator state variables" (A-283) for more information about VSIM-defined variables. System commands To pass commands to the DOS window, use the Tcl exec command: echo The date is [exec date] List processing In Tcl a "list" is a set of strings in curly braces separated by spaces.
VSIM Tcl commands These additional VSIM commands enhance the interface between Tcl and ModelSim, Only brief descriptions are provided here; for more information and command syntax see the "ModelSim Commands" (CR-11).
ModelSim Tcl time commands Conversions Command Description intToTime converts two 32-bit pieces (high and low order) into a 64-bit quantity (Time in ModelSim is a 64-bit integer) RealToTime converts a number to a 64-bit integer in the current Time Scale scaleTime
ModelSim Tcl time commands Arithmetic Command Description addTime
A - ModelSim Variables Appendix contents Variable settings report . . . . . . . . . . . . . . . . . 254 Personal preferences . . . . . . . . . . . . . . . . . 254 Returning to the original ModelSim defaults . . . . . . . . . . . 254 Environment variables . . . . . . . . . . . . 255 Preference variables located in INI and MPF files [Library] library path variables . . . . [vcom] VHDL compiler control variables .
Variable settings report Variable settings report The report command (CR-82) returns a list of current settings for either the simulator state, or simulator control variables. Use the following commands at either the ModelSim or VSIM prompt: report simulator state report simulator control Personal preferences There are several preferences stored by ModelSim on a personal bases, independent of modelsim.ini or modelsim.tcl files.
Environment variables Environment variables Before compiling or simulating, several environment variables may be set to provide the functions described in the table below. The variables are in the autoexec.bat file on Windows 95/98 machines, and set through the System control panel on NT machines. The LM_LICENSE_FILE variable is required, all others are optional.
Environment variables Variable Description STDOUT the VSOUT temp file (generated by the simulator kernel) is deleted when the simulator exits; the file is not deleted if you specify a filename for VSOUT with STDOUT; specifying a name and location (use TMPDIR) for the VSOUT file will also help you locate and delete the file in event of a crash (an unnamed VSOUT file is not deleted after a crash either) TMP specifies the path to a tempnam() generated file (VSOUT) containing all stdout from the simulatio
Environment variables Library mapping with environment variables Once the MY_PATH variable is set, you can use it with the vmap command (CR147) to add library mappings to the current modelsim.ini file. If you’re using the vmap command from DOS prompt type: vmap MY_VITAL %MY_PATH% If you’re using vmap from ModelSim/VSIM prompt type: vmap MY_VITAL \$MY_PATH If you used DOS vmap, this line will be added to the modelsim.ini: MY_VITAL = c:\temp\work If vmap is used from ModelSim/VSIM prompt, the modelsim.
Environment variables may also be referenced from the ModelSim command line or in macros using the Tcl env array mechanism: echo "$env(ENV_VAR_NAME)" Removing temp files (VSOUT) The VSOUT temp file is the communication mechanism between the simulator kernel and the ModelSim GUI. In normal circumstances the file is deleted when the simulator exits. If ModelSim crashes, however, the temp file must be deleted manually.
Preference variables located in INI and MPF files Preference variables located in INI and MPF files ModelSim initialization (INI) and project (MPF) files contain control variables that specify reference library paths, and compiler and simulator settings. When first created, the MPF project file includes all of the variables from the current modelsim.ini file plus an additional [Project] section for project-specific variables.
Preference variables located in INI and MPF files [Library] library path variables Variable name Value range Purpose synopsys any valid path; may include environment variables sets path to the accelerated arithmetic packages [vcom] VHDL compiler control variables Variable name Value range Purpose Default VHDL93 0, 1 if 1, turns on VHDL-1993 off (0) Show_source 0, 1 if 1, shows source line containing error off (0) Show_VitalChecksWarnings 0, 1 if 0, turns off VITAL compliancecheck warnin
Preference variables located in INI and MPF files [vcom] VHDL compiler control variables Variable name Value range Purpose Default Explicit 0, 1 if 1, turns on resolving of ambiguous function overloading in favor of the "explicit" function declaration (not the one automatically created by the compiler for each type declaration) off (0) NoVitalCheck 0, 1 if 1, turns off VITAL compliance checking off (0) IgnoreVitalErrors 0, 1 if 1, ignores VITAL compliance checking errors off (0) NoDebug 0,
Preference variables located in INI and MPF files [vlog] Verilog compiler control variables Variable name Value range Purpose Default Hazard 0, 1 if 1, turns on Verilog hazard checking (orderdependent accessing of global vars) off (0) NoDebug 0, 1 if 1, turns off inclusion of debugging info within design units off (0) Quiet 0, 1 if 1, turns off "loading...
Preference variables located in INI and MPF files [vsim] simulator control variables Variable name Value range Purpose Default AssertionFormat see purpose sets the message to display after a break on assertion; message formats include: %S - severity level %R - report message %T - time of assertion %D - delta %I - instance or region pathname (if available) %% - print ’%’ character "** %S: %R\n Time: %T Iteration: %D%I\n" BreakOnAssertion 0-4 defines severity of assertion that causes a simulation b
Preference variables located in INI and MPF files [vsim] simulator control variables Variable name Value range Purpose Default DelayFileOpen 0, 1 if 1, open VHDL87 files on first read or write, else open files when elaborated off (0) GenerateFormat %s__%d control the format of a generate statement label (don’t quote it) commented out (;) IgnoreError 0,1 if 1, ignore assertion errors off (0) IgnoreFailure 0,1 if 1, ignore assertion failures off (0) IgnoreNote 0,1 if 1, ignore assertion
Preference variables located in INI and MPF files [vsim] simulator control variables Variable name Value range Purpose Default Resolution fs, ps, ns, us, ms, sec - also 10x and 100x simulator resolution; default is ns; this value must be less than or equal to the UserTimeUnit specified below; NOTE - if your delays are truncated, set the resolution smaller ns RunLength positive integer default simulation length in units specified by the UserTimeUnit variable 100 Start up = do ; any
Preference variables located in INI and MPF files [vsim] simulator control variables Variable name Value range Purpose Default WaveSignalNameWidth 0, positive or negative integer controls the number of visible hierarchical regions of a signal name shown in the Wave window (7-164); the default value of zero displays the full name, a setting of one or above displays the corresponding level(s) of hierarchy 0 [Project] project file section (MPF files only) Variable name Value range Purpose Src_Files
Preference variables located in INI and MPF files Spaces in path names For the Src_Files and Work_Libs variables, each element in the list is enclosed within curly braces ({}). This allows spaces inside elements (since Windows allows spaces inside path names). For example a source file list might look like: Src_Files = {$MODELSIM_PROJECT/counter.v} {$MODELSIM_PROJECT/tb counter.v} Where the file tb counter.v contains a space character between the "b" and "c".
Preference variables located in INI and MPF files the name of the directory from which the VCOM compiler or VSIM simulator was invoked. MODEL_TECH is used by the other Model Technology tools to find the libraries. Hierarchical library mapping By adding an "others" clause to your modelsim.ini file, you can have a hierarchy of library mappings. If the ModelSim tools don’t find a mapping in the modelsim.
Preference variables located in INI and MPF files Turning off assertion messages You can turn off assertion messages from your VHDL code by setting a switch in the modelsim.ini file. This option was added because some utility packages print a huge number of warnings. [vsim] IgnoreNote = 1 IgnoreWarning = 1 IgnoreError = 1 IgnoreFailure = 1 Messages may also be turned off with Tcl variables; see "Preference variables located in TCL files" (A-271).
Preference variables located in INI and MPF files Opening VHDL files You can delay the opening of VHDL files with a entry in the INI file if you wish. Normally VHDL files are opened when the file declaration is elaborated. If the DelayFileOpen option is enabled, then the file is not opened until the first read or write to that file.
Preference variables located in TCL files Preference variables located in TCL files ModelSim TCL preference variables give you control over fonts, colors, prompts, window positions and other simulator window characteristics. Preference files, which contain Tcl commands that set preference variables, are loaded before any windows are created, and so will affect all windows. When ModelSim is invoked for the first time, default preferences are loaded from the pref.tcl file.
Preference variables located in TCL files Preference variable arrays Most preference variables are Tcl procedure lists (arrays), grouped by name within the TCL file. A unique array is defined for: • all GUI defaults • each VSIM window type • the library browser • the Code Coverage and Performance Analyzer windows • logic value translations used in the List window (7-128) and Wave window (7-164) • the force command (CR-56) The most common variable array types are listed in the table below.
Preference variables located in TCL files Variable array type Description ListTranslateTable() ListTranslateTable specifies how various enumerations of various types map into the nine logic types that the List and Wave window know how to display. This mapping is used for vectors only; scalars are displayed with the original enum value. The following example values show that the std_logic_1164 types map in a one-to-one manner, and also shows mappings for boolean and Verilog types.
Preference variables located in TCL files Main window preference variables The Main window uses preference variables similar to other ModelSim window to conrol colors and fonts. The variables below control some additional functions.
Preference variables located in TCL files Individual preference variables Though most preference variables occur in arrays, the following individual variables are also found in TCL files. Variable name Value range Purpose DOPATH a colon-separated list of paths to directories used by VSIM to search for simulator command files (DO files); overrides the DOPATH (A-255) environment variable PlotFilterResolution 0.1 + specifies the output resolution for the waveform postscript file; default is 0.
Preference variables located in TCL files Setting Tcl preference variables Preference variable within TCL file may be set in one of two ways. • Setting variables with the GUI (A-276) • Directly editing preference files (A-281) Setting variables with the GUI Use the Main > Options > Edit Preferences menu selection to open the Preferences dialog box shown below. Use the Apply button to set temporary defaults for the current simulation.
Preference variables located in TCL files By Window page The By Window page includes these options: • Window Select the window type to modify; the color and font changes you make apply to all windows of this type. The Source window view allows you to preview source examples for either VHDL or Verilog. When you select the Source window, you can change preferences based on VHDL or Verilog source.
Preference variables located in TCL files • Font Select the Choose button; the Font Selection dialog box opens for your selection. In the Font Selection dialog box, any selection you make automatically updates the By Window page; the Reset button scans your system for fonts and Quit closes the selection box.
Preference variables located in TCL files By Name page The By Name page includes these options: • Preference Select the Preference and Item to change, and then click the Change Value button. Enter the new value into the field provided in the resulting dialog box.
Preference variables located in TCL files In addition to window preferences (listed by window name in the Preference list), you may also set: • Default Set default colors and fonts for menus and tree windows, also fill colors for VHDL (box) and Verilog (arc) structure symbols; these may be changed for individual windows. • Geometry Set the default size and position for the selected window type; used for the geometry of any newly-created window.
Preference variables located in TCL files The By Name page is a graphic representation of the "Preference variable arrays" (A-272) located in the modelsim.tcl preference file. The changes you make in the Preferences dialog box are temporary for the current simulation. Your changes can be saved as permanent defaults by using Main > Options > Save Preferences. The new settings are saved to the current directory in the modelsim.tcl file by default. You may choose a different name for the TCL file if you wish.
Preference variable loading order Preference variable loading order ModelSim .tcl, INI, and MPF files all contain variables that are loaded when you start ModelSim. The files are evaluated for variable settings in the order below. .tcl file variables are evaluated before the design is loaded ModelSim evaluates .tcl files prior to loading a design for simulation. 1 The /modeltech/tcl/vsim/pref.tcl file is always loaded.
Simulator state variables Simulator state variables Unlike other variables that must be explicitly set, simulator state variables return a value relative to the current simulation. Simulator state variables can be useful in commands, especially when used within a ModelSim DO files (macros).
A-284 ModelSim Variables ModelSim Xilinx User’s Manual
B - ModelSim Shortcuts Appendix contents Wave window keyboard shortcuts . . . . . . . . . . . . 285 List window keyboard shortcuts . . . . . . . . . . . . 286 Command shortcuts . . . . . . . . . . . . . . . 286 Command history shortcuts . . . . . . . . . . . . . 287 Mouse and keyboard shortcuts in the Transcript and Source windows . . 287 Right mouse button . . 288 . . . . . . . . . . . . .
Key Action scroll waveform display down by page searches forward (right) to the next transition on the selected signal - finds the next edge searches backward (left) to the previous transition on the selected signal - finds the previous edge opens the find dialog box; search within the specified field in the wave-name pane for text strings List window keyboard shortcuts Using the following keys when the mouse cursor is within the List window will cause the
You may abbreviate command syntax, but there’s a catch. The minimum characters required to execute a command are those that make it unique. Remember, as we add new commands some of the old shortcuts may not work.
Keystrokes Result < left | right - arrow > move the insertion cursor < up | down - arrow > scroll through command history < control - p > move insertion cursor to previous line < control - n > move insertion cursor to next line < control - f > move insertion cursor forward < control - b > move insertion cursor backward < backspace > delete character to the left < control - d >, delete character to the right < control - k > delete to the end of line < control - a >, move
C - Tips and Techniques Appendix contents Running command-line and batch-mode simulations . . . . . . . . . 290 Passing parameters to macros . . . . . . . . . . . . . . . 291 Source code security and -nodebug . . . . . . . . . . . . . . 292 Setting up libraries for group use . . . . . . . . . . . . . . 292 Detecting infinite zero-delay loops . . . . . . . . . . . . . . 293 Modeling memory in VHDL . . . . . . . . . . . . .
Running command-line and batch-mode simulations Running command-line and batch-mode simulations The typical method of running ModelSim is interactive: you push buttons and/or pull down menus in a series of windows in the GUI (graphic user interface). But there are really three specific modes of vsim operation: GUI, command line, and batch. Here are their characteristics: • GUI mode This is the usual interactive mode; it has graphical windows, push-button menus, and a command line in the text window.
Passing parameters to macros Passing parameters to macros In ModelSim, you invoke macros with the do command: Syntax do [ ...] Arguments Specifies the name of the macro file to be executed. Specifies values that are to be passed to the corresponding parameters $1 through $9 in the macro file. Multiple parameter values must be separated by spaces.
Source code security and -nodebug Source code security and -nodebug The -nodebug option on both vcom (CR-106) and vlog (CR-141) hides internal model data. This allows a model supplier to provide pre-compiled libraries without providing source code and without revealing internal model variables and structure. Note: ModelSim’s -nodebug compiler option provides protection for proprietary model information.
Detecting infinite zero-delay loops Detecting infinite zero-delay loops VHDL simulation uses steps that advance simulated time, and steps that do not advance simulated time. Steps that do not advance simulated time are called "delta cycles". Delta cycles are used when signal assignments are made with zero time delay. If a large number of delta cycles occur without advancing time, it is usually a symptom of an infinite zero-delay loop in the design.
Modeling memory in VHDL A simple alternative implementation provides some excellent performance benefits: • storage required to model the memory can be reduced by 1-2 orders of magnitude • startup and run times are reduced • associated memory allocation errors are eliminated The trick is to model memory using variables instead of signals. In the example below, we illustrate three alternative architectures for entity "memory". Architecture "style_87_bad" uses a vhdl signal to store the ram data.
Modeling memory in VHDL architecture style_93 of memory is -----------------------------shared variable ram : ram_type; -----------------------------begin memory: process (cs) variable address : natural; begin if rising_edge(cs) then address := sulv_to_natural(add_in); if (mwrite = ’1’) then ram(address) := data_in; data_out <= ram(address); else data_out <= ram(address); end if; end if; end process memory; -- illustrates a second process using the shared variable initialize: process (do_init) variable add
Modeling memory in VHDL data_out <= ram(address); else data_out <= ram(address); end if; end if; end process; end style_87; architecture bad_style_87 of memory is ---------------------signal ram : ram_type; ---------------------begin memory: process (cs) variable address : natural := 0; begin if rising_edge(cs) then address := sulv_to_natural(add_in); if (mwrite = ’1’) then ram(address) <= data_in; data_out <= data_in; else data_out <= ram(address); end if; end if; end process; end bad_style_87; --------
Modeling memory in VHDL variable n : natural := 0; variable failure : boolean := false; begin assert (x’high - x’low + 1) <= 31 report "Range of sulv_to_natural argument exceeds natural range" severity error; for i in x’range loop n := n * 2; case x(i) is when ’1’ | ’H’ => n := n + 1; when ’0’ | ’L’ => null; when others => failure := true; end case; end loop; assert not failure report "sulv_to_natural cannot convert indefinite std_ulogic_vector" severity error; if failure then return 0; else return n; end
C-298 Tips and Techniques ModelSim Xilinx User’s Manual
Index A architecture simulator state variable 283 argc simulator state variable 283 AssertFile .ini file variable 262 AssertionFormat .ini file variable 263 Assertions selecting severity that stops simulation 213 B Batch mode 290 Break on assertion 213 BreakOnAssertion .ini file variable 263 Breakpoints deleting 152 setting 152 viewing 152 C Cell libraries 71 CheckpointCompressMode .ini file variable 263 CheckSynthesis .
assigning a logical name 29 creating 25 for VHDL design units 44 mapping search rules 31 resource type 24 working type 24 Design units 24 viewing hierarchy 111 Directories moving libraries 31 See also, Libraries DOPATH environment variable 255 DOPATH simulator control variable 275 E Editing in notepad windows 121, 287 in the Main window 121, 287 in the Source window 121, 287 EDITOR environment variable 255 entity simulator state variable 283 Environment variables 255 in PrefMain(file) variable 274 location
Initialization file, see Project files Instantiation label 159 Iteration_limit detecting infinite zero-delay loops 293 IterationLimit .ini file variable 264 K Keyboard shortcuts List window 140, 286 Wave window 187, 285 L _script .
MODELSIM_TCL environment variable 256 MPF file 36 MTI_TF_LIMIT environment variable 255 Multiple drivers on unresolved signal 199 N n simulator state variable 283 Nets adding to the Wave and List windows 149 displaying values in Signals window 144 forcing signal and net values 147 saving values as binary log file 149 viewing waveforms 164 Next and previous edges, finding 187, 285 No space in time literal 198 NoDebug .ini file variable (VCOM) 261 NoDebug .
specifying in List window 136 specifying in Signals window 148 reconstruct RTL-level design busses 101 Records changing values of 161 Refreshing library images 33 Register variables adding to the Wave and List windows 149 displaying values in Signals window 144 saving values as binary log file 149 viewing waveforms 164 Resolution .ini file variable 265 resolution simulator state variable 283 resource library 24 restart 116, 120 RunLength .ini file variable 265 S ScalarOpts .
setting iteration limit 212 setting time resolution 203 Verilog delay modes 71 even order issues 66 hazard detection 67 resolution limit 65 XL compatible simulator options 68 Verilog designs 65 VHDL designs 45 viewing results in List window 128 with VITAL packages 52 simulating with the graphic interface 202 Simulation and Compilation Verilog 54–94 VHDL 43–52 Sorting sorting HDL items in VSIM windows 110 Source code source code security 292 viewing 152 Source directory, setting from source window 153 Source
U Unbound Component 198 UnbufferedOutput .ini file variable 265 UpCase .ini file variable 262 Use 1076-1993 language standard 197 Use clause specifying a library 32 Use explicit declarations only 197 user-defined buses 100 UserTimeUnit .
virtual hide command 101 VITAL compiling and simulating with accelerated VITAL packages 52 obtaining the specification and source code 51 VITAL packages 51 VSIM commands searchLog 103 W Warnings turning off warnings from arithmetic packages 269 Wave window (see also, Windows) 164 WaveSignalNameWidth .
