Technical data

Mixed VHDL/Verilog simulation
8-78 ModelSim EE/SE Tutorial
Notice the hierarchical mixture of VHDL and
Verilog in the design. VHDL levels are indicated
by a square “prefix”, while Verilog levels are
indicated by a circle “prefix.” Try expanding (+)
and contracting (-) the structure layers. You’ll
find Verilog modules have been instantiated by
VHDL architectures, and similar instantiations of
VHDL items by Verilog.
Let’s take another look at the design.
11In the Structure window, click on the Verilog
module c: cache. The source code for the Verilog
module is now shown in the Source window.
12We’ll use ModelSim’s Find function to locate the
declaration of cache_set within cache.v.
From the Source window menu select: Edit >
Find > Source Text; the Find in dialog box is
displayed.
In the Find: field, type
cache_set and click Find
Next. The cache_set
declaration is now displayed
in the Source window. (Click
Close to dismiss the Find in:
dialog box.)
Note that the declaration of cache_set is a VHDL entity instantiated within the
Verilog file cache.v.