Technical data

ModelSim EE/SE Tutorial 8-73
Lesson 8 - Mixed VHDL/Verilog simulation
You must be using ModelSim /PLUS for this lesson.
The goals for this lesson are:
• Compile multiple VHDL and Verilog files.
• Simulate a mixed VHDL and Verilog design.
• List VHDL signals and Verilog nets and registers.
• View the design in the Structure window.
• View the HDL source code in the Source window.
1 First, return to the directory you created in Lesson 2 -Basic VHDL simulation.
cd <directory_name>
Next copy the VHDL and Verilog example files to the directory:
<install_dir>\modeltech\examples\mixedHDL\*.vhd
<install_dir>\modeltech\examples\mixedHDL\*.v
2 Start ModelSim with this command from the UNIX/DOS prompt (or modelsim.exe for
Windows):
vsim -gui
This opens the ModelSim Main window without loading a design.