Technical data

Basic Verilog simulation
ModelSim EE/SE Tutorial 7-65
The Structure window shows the hierarchical
structure of the design. By default, only the top
level of the hierarchy is expanded. You can
navigate within the hierarchy by clicking on any
line with a "+" (expand) or "-" (contract)
symbol. The same navigation technique works
anywhere you find these symbols within
ModelSim.
By clicking the "+" next to dut: counter (as
shown here) you can see all three hierarchical
levels: test_counter, counter and a function
called increment. (If test_counter is not
displayed you simulated counter instead of
test_counter.)
13 Click on Function increment and notice how other VSIM windows are automatically
updated as appropriate.
Specifically, the Source window displays the Verilog code at the hierarchical level
you selected in the Structure window. The source-file name is also displayed in
the Source window title bar.
Using the Structure window in this way is analogous to scoping commands in
interpreted Verilogs.
For now, make sure the test_counter module is showing in the Source window by
clicking on the top line in the Structure window.
14 Now you will exercise different Run functions from the toolbar.
15 Select Run button on the Main toolbar. This causes the simulation to run and then stop
after 100 ns (the default simulation length).
(PROMPT: run) (MENU: Run > Run 100 ns)