Technical data

Basic Verilog simulation
ModelSim EE/SE Tutorial 7-63
The Load Design dialog box allows you to select a design unit to simulate from
the specified library. You can also select the resolution limit for the simulation.
The default library is work and the default resolution is 1 ns.
7 Design Unit: test_counter and click Load to accept these settings.
8 Bring up the Signals, List and Wave windows by entering the following line at the
VSIM prompt within the Main window:
view signals list wave
(Main MENU: View > <window name>)
9 To list the top-level signals, move the pointer to the Signals window and make this
View menu selection: View > List > Signals in Region.
(PROMPT: add list \counter\*)
10 Now let’s add signals to the Wave window with ModelSim’s drag and drop feature.
In the Signals window, control-click on each of the clk, rst, and count signals to
make a group selection. Click and hold on the group one more time, then drag it
to either the pathname or the values pane of the Wave window.