Technical data

Basic Verilog simulation
7-60 ModelSim EE/SE Tutorial
4 Before you compile a source file, you’ll need a design library to hold the compilation
results. To create a new design library, make this menu selection in the Main window:
Design > Create a New Library.
(PROMPT: vlib work)
In the Create a New Library dialog
box, select Create: a new library
and a logical mapping to it.
Make sure Library: indicates
work, then select OK. This
creates a subdirectory named work
- your design library - within the
current directory. This
subdirectory contains a special file
named _info. (Do not create these
using UNIX or Windows
commands—always use the
Library menu or the vlib
command from either the
ModelSim or UNIX/DOS
prompt.)