Technical data

ModelSim EE/SE Tutorial 7-59
Lesson 7 - Basic Verilog simulation
You must be using ModelSim/PLUS or ModelSim/VLOG for this lesson.
The goals for this lesson are:
• Compile a Verilog design.
• Examine the hierarchy of the design.
• List signals in the design.
• Change list attributes.
• Set a breakpoint.
• Add and remove cursors in the waveform display.
If you’ve completed any previous VHDL lesson you’ll notice that the Verilog and
VHDL simulation processes are almost identical.
1 Create and change to a new directory to make it the current directory.
2 Copy the Verilog files (files with ".v" extension) from the
\<install_dir>\modeltech\examples directory into the current directory.
Before you can compile a Verilog design, you need to create a design library in
the new directory. If you are only familiar with interpreted Verilog simulators
such as Cadence Verilog XL this will be a new idea for you. Since ModelSim is a
compiled Verilog, it requires a target design library for the compilation. ModelSim
can compile both VHDL and Verilog code into the same library if desired.
3 Invoke ModelSim:
for UNIX at the shell prompt:
vsim -gui
for Windows - your option - DOS prompt, shortcut, or Start menu:
modelsim.exe
This opens the ModelSim Main window without loading a design.