Technical data

Debugging a VHDL design
3-32 ModelSim EE/SE Tutorial
vmap work library_2
ModelSim modifies the modelsim.ini file for you.
5 Start the simulator by selecting Design > Load New Design from the Main window,
or by clicking the Load Design icon. The Load Design dialog box is displayed, as
shown here.
6
Perform the following steps in this
dialog box:
• Make sure that the simulator
resolution is default. (The default
resolution is ns.)
• Look in the Design Unit scroll
box and select the configuration
named test_adder_structural.
• Click Load to accept the settings.
(PROMPT: vsim -t ns
work.test_adder_structural)
7
To open all of the VSIM windows,
enter the following command in the
Main window at the VSIM prompt:
view *
(Main MENU: View > All)
ModelSim will open all the
windows in the positions you
left them at the end of the last
exercise if no one has run the
simulator since then.
8 Drag and drop the top-level signals to the List window in the following manner: make
sure the hierarchy is not expanded (no minus boxes), select all signals in the Signals
window with Edit > Select All, then drag the selected signals to the List window.
(Signals MENU: View > List > Signals in Region) (PROMPT: add list *)