Technical data

ModelSim EE/SE Tutorial 3-31
Lesson 3 - Debugging a VHDL design
The goals for this lesson are:
• Show an example of a VHDL testbench - a VHDL architecture that instantiates
the VHDL design units to be tested, provides simulation stimuli, and checks the
results.
• Map a logical library name to an actual library.
• Change the default run length.
• Recognize assertion messages in the command window.
• Change the assertion break level
• Restart the simulation run using the restart command.
• Examine composite types displayed in the VSIM Variables window.
• Change the value of a variable.
• Use a strobe to trigger lines in the VSIM List window.
• Change the radix of signals displayed in the VSIM List window.
1 Return to the directory you created in Lesson 2 - Basic VHDL simulation (p21), and
invoke ModelSim:
for UNIX at the shell prompt:
vsim -gui
for Windows - your option - DOS prompt, shortcut, or Start menu:
modelsim.exe
2 Enter the following command at the ModelSim prompt to create the a new library:
vlib library_2
3 Compile the source files into the new library by entering this command at the system
prompt:
vcom -work library_2 gates.vhd adder.vhd testadder.vhd
4 Now let’s map the new library to the work library. To create a mapping you can edit
the [Library] section of the modelsim.ini file, or you can create a logical library name
with the vmap command: