ModelSim EE/SE Tutorial Version 5.
ModelSim /VHDL, ModelSim /VLOG, ModelSim /LNL, and ModelSim /PLUS are produced by Model Technology Incorporated. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of Model Technology. The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology.
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Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Before you begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Lesson 1 - Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Lesson 2 - Basic VHDL simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Lesson 3 - Debugging a VHDL design . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction Chapter contents Software versions . . . . . . . . . . . . . . . . . . 7 ModelSim’s graphic interface . . . . . . . . . . . . . . . . 8 Standards supported . . . . . . . . . . . . . . . . . . . 8 Assumptions . . . . . . . . . . . . . . . . . . . 8 Where to find our documentation . . . . . . . . . . . . . . . 9 . . .
ModelSim’s graphic interface While your operating system interface provides the window-management frame, ModelSim controls all internal-window features including menus, buttons, and scroll bars.
We also assume that you have a working knowledge of VHDL and Verilog. Although ModelSim is an excellent tool to use while learning HDL concepts and practices, this document is not written to support that goal. Comments Comments and questions about this manual and ModelSim software are welcome. Call, write, or fax or email: Model Technology Incorporated 10450 SW Nimbus Avenue, Bldg. R-B Portland, OR 97223-4347 USA phone: 503-641-1340 fax: 503-526-5410 email: manuals@model.com home page: http://www.model.
Document Format How to get it ModelSim EE Tutorial PDF online from the ModelSim Help menu in the EE Documentation group, or find ee_tutor.pdf in the /modeltech/docs directory on the CD-ROM, or hard drive after installation, also available from the Support page of our web site: www.model.
Before you begin Preparation for some of the lessons leaves certain details up to you. You will decide the best way to create directories, copy files and execute programs within your operating system. (When you are operating the simulator within ModelSim’s GUI, the interface is consistent for all platforms.) Additional details for VHDL, Verilog, and mixed VHDL/Verilog simulation can be found in the ModelSim Reference Manual. (See "Where to find our documentation" (p9).
Shortcut Description click on prompt left-click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor his or history shows the last few commands (up to 50 are kept) Reusing commands from the Main transcript ModelSim’s Main transcript may be saved, and the resulting file used as a DO (macro) file to replay the transcribed commands. You can save the transcript at any time before or during simulation.
Lesson 1 - Creating a Project The goals for the first lesson are: • Explore the Welcome to ModelSim dialog box features. • Create a project (.mpf file). Upon opening ModelSim 5.3 for the first time, you will see a Welcome to ModelSim dialog box. (If this screen is not available, you can enable it by selecting Help > Enable Welcome from the Main window.
Creating a Project Creating a Project With the 5.3 release, ModelSim incorporates the file extension .mpf to denote project files. In past releases the modelsim.ini file (the system initialization file) was used as the project file. A project is a collection entity for an HDL design under specification or test. At a minimum, it has a root directory, a work library and session state that is stored in a .mpf file located in the project's root directory.
Creating a Project Clicking the Create a Project button opens the Create a New Project dialog box and a project creation wizard. The wizard helps you through each step of creating a new project. It provides the option of entering Verilog or VHDL source file descriptions, then helps you load the project. The Create a New Project dialog box can also be accessed by selecting File > New > New Project from the ModelSim Main window.
Creating a Project Note: A project's .mpf file is always located in the project's directory. 6 Once you have specified enough information to copy an existing project, the OK button is selectable. Selecting OK causes the project directory to be created with a default working library. You will then be asked if you want to make this project your current project. Click Yes. 7 In the dialog box that asks if you want to create a new HDL source file for your project, click No.
Creating a Project 8 Select Options > Edit Project. This opens the Edit Project dialog box. Click the down arrow next to the Source File entry field and select the source counter.vhd. With the source file selected, the Compile button becomes available. 9 Click the Compile button in the Edit Project dialog box. With a source file compiled, the Add to Library button becomes available. 10 Click Add to Library, then Done, in the Edit Project dialog box.
Creating a Project The Edit Project dialog also allows you to import a new source file into libraries local to the project. Note: The process of Compile and Add to Library creates a script (DO file) that will recompile the entire project. You must Add to Library after each Compile to create a proper script. To recompile a project use the Main > Design > Compile Project menu selection.
Creating a Project This completes the process of creating a project by copying an existing project. The newly created project will be open for use in the Main window. You can now elect to leave ModelSim or edit this project’s HDL components until the project is completely specified and all files compile into libraries local to the project.
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Lesson 2 - Basic VHDL simulation The goals for this lesson are: • Create a library. • Compile a VHDL file. • Start the simulator. • Understand the basic VSIM windows, mouse, and menu conventions. • Run VSIM using the run command. • List some signals. • Use the waveform display. • Force the value of a signal. • Single-step through a simulation run. • Set a breakpoint. • Use the Wave window. 1 Start out by creating a new directory for this exercise (in case other users will be working with these lessons).
Basic VHDL simulation In the Create a New Library dialog box select Create: a new library and a logical mapping to it. Make sure Library: indicates work, then select OK. This creates a subdirectory named work - your design library - within the current directory. This subdirectory contains a special file named _info. (Do not create these using UNIX or Windows commands—always use the Library menu or the vlib command from either the ModelSim or UNIX/DOS prompt.
Basic VHDL simulation Complete the compilation by selecting counter.vhd from the file list and clicking Compile. Select Done when you are finished. You can compile multiple files in one session from the file list. Individually select and Compile the files in the order required by your design.
Basic VHDL simulation The Load Design dialog box allows you to select the library and the top-level design unit to simulate. You can also select the resolution limit for this simulation.
Basic VHDL simulation 6 Select the entity counter and choose Load to accept these settings. 7 Now you can open all of the VSIM windows with this Main window menu selection: View > All. (PROMPT: view *) 8 To display the top-level signals in the List window, select the Signals window and make this Signal menu selection: View > List > Signals in Region. (PROMPT: add list /counter/*) 9Next add top-level signals to the Wave window with a similar Signals menu selection: View > Wave > Signals in Region.
Basic VHDL simulation Note how the Run Length selector on the toolbar now indicates 100 (ns is the current default resolution). You will see the effects of this force command as soon as you tell the simulator to run. 11 Now you will exercise two different Run functions from the toolbar buttons on either the Main or Wave window. (The Run functions are identical in the Main and Wave windows.) Select the Run button first. When the run is complete, select Run All. Run.
Basic VHDL simulation The arrow in the Source window points to the next HDL statement to be executed. (If the simulator is not evaluating a process at the time the Break occurs, no arrow will be displayed in the Source window.) Next, you will set a breakpoint in the function on line 18. 13 Move the pointer to the VSIM Source window. Using the vertical scroll bar, scroll until line 18 is visible. Click at or near line number 18 to set the breakpoint.
Basic VHDL simulation 14 Select the Continue Run button to resume the run that you interrupted. VSIM will hit the breakpoint, as shown by an arrow in the VSIM Source window and by a Break message in the Main window. Also note that the parameters and variables within the function are displayed in the VSIM Variables window. (PROMPT: run -continue) (MENU: Run > Continue) 15 Click the Step button to single-step through the simulation. Notice that the values change in the VSIM Variables window.
Basic VHDL simulation In the Wave window, you can use cursors to: • probe for values - Signal values update whenever you move the cursor. • find signal transition times - Click a signal edge, the cursor displays the time. • measure time intervals - Time is displayed between two cursors.
Basic VHDL simulation 17 When you’re done experimenting, quit the simulator by entering the command: quit -force This command exits VSIM without saving data. Your window positions will be saved in the modelsim.ini file and the windows will close. (Refer to the ModelSim Reference Manual for additional information on the modelsim.ini file.
Lesson 3 - Debugging a VHDL design The goals for this lesson are: • Show an example of a VHDL testbench - a VHDL architecture that instantiates the VHDL design units to be tested, provides simulation stimuli, and checks the results. • Map a logical library name to an actual library. • Change the default run length. • Recognize assertion messages in the command window. • Change the assertion break level • Restart the simulation run using the restart command.
Debugging a VHDL design vmap work library_2 ModelSim modifies the modelsim.ini file for you. 5 Start the simulator by selecting Design > Load New Design from the Main window, or by clicking the Load Design icon. The Load Design dialog box is displayed, as shown here. 6 Perform the following steps in this dialog box: • Make sure that the simulator resolution is default. (The default resolution is ns.) • Look in the Design Unit scroll box and select the configuration named test_adder_structural.
Debugging a VHDL design 9 To add top-level signals to the Wave window, enter the command: add wave * (Signals MENU: View > Wave > Signals in Region) (DRAG&DROP) 10 Now change the default simulation run length to 1000 (ns) with the run length selector on the Main toolbar. Click on the field to edit the number to 1000 (notice how the arrows allow you to change the run length in increments). (Main MENU: Options > Simulation > Defaults) 11 Next, you will run the simulator.
Debugging a VHDL design 12 First, change the simulation assertion options. Make this Main menu selection: Options > Simulation. 13 Select the Assertions page. Change the selection for Break on Assertion to Error and click OK. This will cause the simulator to stop at the HDL statement after the assertion is displayed. 14 To restart the simulation select the Restart button on the Main toolbar.
Debugging a VHDL design 15 From the Main toolbar select the Run button. (Main MENU: Run > Run 1000 ns) (PROMPT: run) Notice that the arrow in the Source window is pointing to the statement after the assertion. 16 If you turn to the Variables window now, you can see that i = 6. This indicates that the simulation stopped in the sixth iteration of the test pattern’s loop.
Debugging a VHDL design 17 Expand the variable named test_patterns by clicking the [+]. (You may need to resize the window for a better view.) 18 Also expand the sixth record in the array test_patterns(6), by clicking the [+]. The Variables window should be similar to the one below. The assertion shows that the Signal sum does not equal the sum field in the Variables window. Note that the sum of the inputs a, b, and cin should be equal to the output sum. But there is an error in the test vectors.
Debugging a VHDL design 21 In the Variables window, expand test_patterns and test_pattern(6) again. Then highlight the .sum record by clicking on the variable name (not the box before the name) and then use the Edit > Change menu selection. 22 Select the last four bits in the value field 1000 by dragging the pointer across them. Then replace them with 0111, and click Change. (Note that this is a temporary edit, you must use your text editor to permanently change the source code.
Debugging a VHDL design 25 Perform these steps on Triggers page in the Modify Display Properties (list) dialog box: • Deselect Trigger On: Signals to disable triggering on signals. • Select Trigger On: Strobe to enable the strobe. • Enter 100 in the Strobe Period field. • Enter 70 in the First Strobe at field. • Click OK to accept the settings. 26 Your next action will be to change the radix for a, b, and sum to decimal. Make this List window menu selection: Prop > Signal Props.
Debugging a VHDL design 27 In the List window select the signal you want to change, then make the property changes in the dialog box. Make the following property changes: • Select signal a, then click Decimal, then click Apply. • Select signal b, then click Decimal, then Apply. • Select signal sum, then click Decimal, then OK. This brings you to the end of this lesson, but feel free to experiment further with the menu system.
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Lesson 4 - Running a batch-mode simulation The goals for this lesson are: • Run a batch-mode VHDL simulation. • Execute a macro (DO) file. • View a saved simulation. You’ll work this lesson from a DOS or UNIX prompt. Note: Batch-mode simulations must be run from a DOS or UNIX prompt. 1 To set up for this lesson you’ll need to create a new directory and make it the current directory. Copy this file into your new directory: \\modeltech\examples\counter.
Running a batch-mode simulation 7 To run the batch-mode simulation, enter the following command: vsim -wav saved.wav counter < yourfile This is what you just did in Step 7: • invoked the VSIM simulator on a design unit called "counter" • the -wav switch instructed the simulator to save the simulation results in a log file named saved.wav • used the contents of yourfile to specify that values are to be listed in decimal, to execute a stimulus file called stim.
Lesson 5 - Executing commands at startup The goals for this lesson are: • Specify the design unit to be simulated on the command line. • Edit the modelsim.ini file. • Execute commands at startup with a DO file. Start this lesson from either the UNIX or DOS prompt. 1 For this lesson, you will use a macro (DO) file that provides startup information. For convenience, a startup file has been provided with the ModelSim program.
Executing commands at startup Also notice that all the windows are open. This is because the view * command is included in the startup macro. 5 If you plan to continue with the following practice sessions, keep ModelSim running. If you would like to quit the simulator, enter the following command at the VSIM prompt: quit -force 6 5-44 You won’t need the startup.do file for any other examples, so use your text editor to comment out the "Startup" line in modelsim.ini.
Lesson 6 - Tcl/Tk and ModelSim This lesson is divided into several Tcl examples intended to give you a sense of Tcl/Tk’s function within ModelSim. The examples include a custom simulation interface created with Tcl/Tk. You must be using ModelSim /PLUS or ModelSim /VHDL to complete these exercises. The goals for this lesson are: Example 1 - Create a "hello world" button widget. (p52) Example 2 - Add a procedure that gets called by a button push.
Tcl/Tk and ModelSim ModelSim generates Tcl commands and passes them to the Tcl parser for execution. Commands may be generated by reading characters from an input source, or by associating command strings with ModelSim’s user interface features, such as menu entries, buttons, or keystrokes. When the Tcl library receives commands it parses them into component fields and executes built-in commands directly. For commands implemented by ModelSim, Tcl calls back to the application to execute the commands.
Tcl/Tk and ModelSim The custom-traffic-light interface The subject of our main Tcl/Tk lesson is a simple traffic-light controller. The system is comprised of three primary components: a state machine, a pair of traffic lights, and a pair of traffic sensors. The components are described in three VHDL files: traffic.vhd (the state machine), queue.vhd (the traffic arrival queue) and tb_traffic.vhd (the testbench).
Tcl/Tk and ModelSim The result is a traffic intersection interface similar to this illustration: wm widget Calls to the operating system window manager to create the "traffic" window. frame and scale widget A scale widget within a frame widget creates an analog entry device for a minimum to a maximum value and invokes the VSIM force command canvas widget The background, lines and traffic lights are created with the canvas widget.
Tcl/Tk and ModelSim Tk widgets The intersection illustration points out several Tcl/Tk "widgets". A widget is simply a user interface element, like a menu or scrolled list. Tk widgets are referenced within Tcl procedures to create graphic interface objects. The Tk tool box comes with several widgets, additional widgets can be created using these as a base.
Tcl/Tk and ModelSim examples ready-to-run in the tcl_tutorial\solutions directory. Invoke these commands from the ModelSim prompt to run the intersection: cd solutions do traffic.do Viewing files If you would like to view the source for any of the Tcl files in our examples, use the notepad command at either the ModelSim or VSIM prompt. notepad Most files are opened in read-only mode by default; you can edit the file by deselecting read only from the notepad Edit menu.
Tcl/Tk and ModelSim mouse), or middle (3 button mouse). You can also select a ModelSim or VSIM prompt from the Main transcript to paste a previous command to the current command line. Make a transcript DO file You can rerun the commands executed during the current session with a Do file created from the Main transcript. Make the DO file by saving the transcript with the File > Save Main As menu selection at any time during the exercises. Run the DO file to repeat the commands (do ).
Tcl/Tk and ModelSim Example 1 - Create a "hello world" button widget. Before you begin the examples make sure you have completed "Preparing for the Tcl/Tk examples" (p51). In this example you will study a "hello world" button that prints a message when pressed. 1 Source the Tcl file from the ModelSim prompt: source hello.tcl then run the procedure defined within hello.tcl: hello_example The file hello.tcl was read into the VSIM Tcl interpreter.
Tcl/Tk and ModelSim 2 Drag the mouse across the buttons and notice what happens in the Main transcript. Push one of the buttons; you will see an error dialog box. You can solve this problem by modifying the images.tcl file. 3 To view the source file press the See Source Code button at the bottom of the image display or invoke notepad at the ModelSim prompt: notepad images.tcl You’ll find that the pushme procedure is missing; it’s commented out in images.tcl.
Tcl/Tk and ModelSim source intersection.tcl draw_intersection 2 From the ModelSim prompt, use the procedure set_light_state to change the color of the lights: set_light_state green .traffic.i.ns_light set_light_state green .traffic.i.ew_light You can use the Copy and Paste buttons on the Main toolbar to help build instructions from previous commands. 3 View the source code with this command at the ModelSim prompt: notepad intersection.
Tcl/Tk and ModelSim and indicates the next line to be executed. (If the simulator is not evaluating an executable process when the break occurs, the Source window will not open.) Only the East/West lights are working. You can make both lights work by editing the lights.tcl file. 6 Edit lights.tcl with the notepad to add a when statement for the North/South light. notepad lights.tcl You need to add this because the current statement is for the East/West light only. You’ll find the solution commented.
Tcl/Tk and ModelSim The update is accomplished by using a when statement. 9 After you have added your North/South widget, run your program by invoking this command: source queues.tcl draw_queues According to the traffic indicators, the cars are leaving the intersection at the same rate. That seems fair, but if you are designing an intersection that responds to the traffic flow into the intersection you might want to change the light cycles.
Tcl/Tk and ModelSim (add wave *). You can also change the run length in the Main window. Try using the Run buttons in the Main window and the intersection window. Keep the intersection simulation running to complete the next example. If you want to recreate the final intersection environment quickly, invoke these commands from the ModelSim prompt (after "Preparing for the Tcl/Tk examples" (p51)). cd solutions do traffic.do Example 4 - Draw a state machine that represents the simulation.
Tcl/Tk and ModelSim 5 Reuse the original commands when you're ready to run the state machine (remember, to copy a previous command to the current command line, select the previous ModelSim prompt): source state-machine.tcl draw_state_machine Notice the changes. Try some additional changes if you wish. This is the end of the Tcl/Tk examples. Continue to modify and test the examples if you wish; you can recover the original files at any time in the tcl_tutorial\originals directory.
Lesson 7 - Basic Verilog simulation You must be using ModelSim/PLUS or ModelSim/VLOG for this lesson. The goals for this lesson are: • Compile a Verilog design. • Examine the hierarchy of the design. • List signals in the design. • Change list attributes. • Set a breakpoint. • Add and remove cursors in the waveform display. If you’ve completed any previous VHDL lesson you’ll notice that the Verilog and VHDL simulation processes are almost identical.
Basic Verilog simulation 4 Before you compile a source file, you’ll need a design library to hold the compilation results. To create a new design library, make this menu selection in the Main window: Design > Create a New Library. (PROMPT: vlib work) In the Create a New Library dialog box, select Create: a new library and a logical mapping to it. Make sure Library: indicates work, then select OK. This creates a subdirectory named work - your design library - within the current directory.
Basic Verilog simulation Note: Remember, a library directory should not be created using UNIX/DOS commands - always use the Main Design menu or the vlib command. Next, you’ll compile the Verilog design. The example design consists of two Verilog source files, each containing a unique module. The file counter.v contains a module called counter, which implements a simple 8-bit binary up-counter. The other file, tcounter.v, is a testbench module (test_counter) used to verify counter.
Basic Verilog simulation Note: The order in which you compile the two Verilog modules is not important (other than the sourcecode dependencies created by compiler directives). This may again seem strange to Verilog XL users who understand the possible problems of interface checking between design units, or compiler directive inheritance. ModelSim defers such checks until the design is loaded by VSIM (the HDL simulator). So it doesn't matter here if you choose to compile counter.v before or after tcounter.
Basic Verilog simulation The Load Design dialog box allows you to select a design unit to simulate from the specified library. You can also select the resolution limit for the simulation. The default library is work and the default resolution is 1 ns. 7 Design Unit: test_counter and click Load to accept these settings.
Basic Verilog simulation HDL items can also be copied from one window to another (or within the Wave and List windows) with the Edit > Copy and Edit > Paste menu selections. You can also delete selected items with the Edit > Delete selection. 11 Next open the Structure and Source windows. From the Main window make these menu selections: View > Structure and View > Source.
Basic Verilog simulation The Structure window shows the hierarchical structure of the design. By default, only the top level of the hierarchy is expanded. You can navigate within the hierarchy by clicking on any line with a "+" (expand) or "-" (contract) symbol. The same navigation technique works anywhere you find these symbols within ModelSim. By clicking the "+" next to dut: counter (as shown here) you can see all three hierarchical levels: test_counter, counter and a function called increment.
Basic Verilog simulation 16 Next change the run length to 500 on the Run Length selector and select the Run button again. shows the last transition of the selected signal Now the simulation has run for a total of 600ns (the default 100ns plus the 500 you just asked for). A status bar reflects this information at the bottom of the Main window. 17 The last command you executed (run 500) caused the simulation to advance for 500ns. You can also advance simulation to a specific time.
Basic Verilog simulation Your Source window won’t look exactly like this illustration because your simulation very likely stopped at a different point. Next we'll take a brief look at some interactive debug features of the ModelSim environment. To start with, let's see what we can do about the way the List window presents its data. 20 In the List window select /test_counter/count. From the List window menu bar select Prop > Signal Props. The Modify Signal Properties (list) dialog box is opened.
Basic Verilog simulation Select a display radix of Decimal for the signal count. Click OK. This causes the List window output to change; the count signal is now listed in decimal rather than the default binary. 21 Let’s set a breakpoint at line 30 in the counter.v file (which contains a call to the Verilog function increment). To do this, select dut: counter in the Structure window. Move the cursor to the Source window and scroll the window to display line 30.
Basic Verilog simulation 22 Select the Run -all button from the Main toolbar to resume execution of the simulation. (PROMPT: run -all) (Main MENU: Run -All) When the simulation hits the breakpoint, it stops running, highlights the Source window with an arrow, and issues a Break message in the Main window. 23 Typically when a breakpoint is reached you will be interested in one or more signal values. You have several options for checking values.
Basic Verilog simulation This causes the debugger to step over the function call on line 30. The Step button on the toolbar would have single-stepped the debugger, including each line of the increment function. 25 Experiment by yourself for awhile; setting and clearing breakpoints as well as Step’ing and Step Over’ing function calls until you feel comfortable with the operation of these commands. 26 Now let’s get a Wave window view of the simulation.
io ne us tra xt ns tra zo iti ns on om iti o in n zo 2 om x ou t2 zo x om ar e zo om a fu ll fin d fin d pr ev so r cu r so e cu r le t de d ad These Wave window buttons give you quick access to zooming and cursor placement. r Basic Verilog simulation Click and drag with the center mouse button (3-button) or right mouse button (2-button) to zoom the display.
Basic Verilog simulation Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display. Clicking anywhere in a track selects that cursor and brings it to the mouse position. The cursors are designed to snap to the closest wave edge to the left of the mouse pointer. You can position a cursor without snapping by dragging in the area below the waveforms. 29 Experiment with using the cursors, scrolling, and zooming.
Lesson 8 - Mixed VHDL/Verilog simulation You must be using ModelSim /PLUS for this lesson. The goals for this lesson are: • Compile multiple VHDL and Verilog files. • Simulate a mixed VHDL and Verilog design. • List VHDL signals and Verilog nets and registers. • View the design in the Structure window. • View the HDL source code in the Source window. 1 First, return to the directory you created in Lesson 2 -Basic VHDL simulation.
Mixed VHDL/Verilog simulation 3 Let’s create a new library to hold the mixed design. Make this menu selection in the Main window: Design > Create a New Library. (PROMPT: vlib mixed) In the Create a New Library dialog box select Create: a new library only. In the Library: field type mixed, then select OK. This creates a subdirectory named mixed (your design library) within the current directory. The library contains a special file named _info that is created with the library.
Mixed VHDL/Verilog simulation 4 Now you can map the new library to the work library. From the Main menu select Design > Browse Libraries. In the Library Browser select the work library, then Edit. (PROMPT: vmap work mixed) This opens the Edit Library dialog box; where you can set the library mapping between work and mixed. Type mixed into the Path: field, then click OK. Now you’re ready to compile the design. 5 Compile the HDL files by selecting the Compile button on the toolbar: (PROMPT:vlog cache.
Mixed VHDL/Verilog simulation A group of Verilog files can be compiled in any order. Note, however, in a mixed VHDL/Verilog design the Verilog files must be compiled before the VHDL files. Compile the source, by double-clicking each of these Verilog files in the file list (this invokes the Verilog compiler, vlog): • cache.v • memory.v • proc.v 6 Depending on the design, the compile order of VHDL files can be very specific. In the case of this lesson, the file top.vhd must be compiled last.
Mixed VHDL/Verilog simulation On the Design tab select the top entity and click Load. 8 From the Main menu select View > All to open all ModelSim windows. (PROMPT: view *) 9 This time you will use the VSIM command line to add all of the HDL items in the region to the List and Wave windows: add list * add wave * (Signals MENU: View > List > Signals in Region) (Signals MENU: View > Wave > Signals in Region) 10 Take a look at the Structure window.
Mixed VHDL/Verilog simulation Notice the hierarchical mixture of VHDL and Verilog in the design. VHDL levels are indicated by a square “prefix”, while Verilog levels are indicated by a circle “prefix.” Try expanding (+) and contracting (-) the structure layers. You’ll find Verilog modules have been instantiated by VHDL architectures, and similar instantiations of VHDL items by Verilog. Let’s take another look at the design. 11In the Structure window, click on the Verilog module c: cache.
Mixed VHDL/Verilog simulation 13 Now click on the line "s0: cache_set(only)" in the Structure window. The Source window now shows the VHDL code for the cache_set entity.
Mixed VHDL/Verilog simulation Before you quit, try experimenting with some of the commands you’ve learned from Lesson 1. Note that in this design, “clk” is already driven, so you won’t need to use the force command.
Lesson 9 - Simulating with Performance Analyzer This lesson introduces the Performance Analyzer and shows you how the major Performance Analyzer commands are used. It is designed to demonstrate how the Performance Analyzer can be used to improve simulation performance. You must be using ModelSim EE Special Edition for this lesson. The goals for this lesson will be to: • Run a simulation with the Performance Analyzer OFF and note the simulation run time.
Simulating with Performance Analyzer vcom ringrtl.vhd testring.vhd config_rtl.vhd (MENU: Design > Compile) 6 Use the vsim command to load the design configuration. vsim work.test_bench_rtl (MENU: Design > Load New Design) 7 Now, run the supplied DO file – timerun.do. This file runs the simulation and displays the total run time in the transcript area of the Main window. This test will take a minute or so. do timerun.do Take a look at the commands in the timerun.do file.
Simulating with Performance Analyzer Make a note of the run time of the simulation. (Your run time will depend on the processing speed of your system and may differ from the run time shown here.) Now we’ll reset the simulation to time zero so that the simulation can be timed with the Performance Analyzer ON. 8 Restart the simulation restart -f 9 Use the profile on command to turn on the Performance Analyzer. profile on 10 Now use the timerun.do file again to run the simulation. do timerun.
Simulating with Performance Analyzer Notice that the overhead of running the Performance Analyzer is very small (your results may differ from the results shown here), even with over 5000 samples of the simulation run acquired. 11 Display the Hierarchical Profile output. view_profile (MENU: View > Other > Hierarchical Profile) Note that two lines – retrieve.vhd:35 and store.vhd:43 – are taking the majority of the simulation time.
Simulating with Performance Analyzer Speed up the simulation The information provided by the Performance Analyzer can be used to speed up the simulation. Double click the pathname for store.vhd:43 and retrieve.vhd:35 and view the source code. In both cases, the source includes a loop which could have an exit. 12 Modify the loops to include exits inside the IF statements, or compile the following files included for that purpose – store_exit.vhd and retrieve_exit.vhd. vcom retrieve_exit.vhd store_exit.
Simulating with Performance Analyzer (MENU: Design > Compile) 14 Reset the simulation to time zero and restart with the modified files. restart -f 15 Run timerun.do again and note the difference in run time. do timerun.do Run time has been cut almost in half by inserting exits in the loops. 16 Take another look at the Performance Analyzer data.
Simulating with Performance Analyzer A lot of time is still being spent in the loops. To further reduce simulation time, these loops can be replaced by indexing an array. 17 Remove the loops and add an array, or compile the following files with the modifications already done. vcom retrieve_array.vhd store_array.vhd (MENU: Design > Compile) 18 Compile the top level blocks and configuration files again. vcom ringrtl.vhd testring.vhd config_rtl.
Simulating with Performance Analyzer 20 Run timerun.do again and note the difference in simulation run time. Your simulation time may differ from that shown here, but the new run should be very fast – approximately ten times faster than the original simulation time. do timerun.do 21 Look, again, at the Hierarchical Profile of simulation performance and you will see more lines showing.
Simulating with Performance Analyzer Update icon %Under filter 22 Set the Under% filter to "2" and click the Update icon. This will filter out all usage values below 2%.
Simulating with Performance Analyzer 23 Take a look at the Ranked Profile view.
Simulating with Performance Analyzer 24 Use the report command to output a file with the profile data. profile report -hierarchical -file hier.
Simulating with Performance Analyzer This command outputs a hierarchical profile of performance data with the file name hier.rpt. 25 Quit the simulator.
Lesson 10 - Simulating with Code Coverage This lesson will introduce ModelSim’s Code Coverage feature, detail the use of the major Code Coverage commands, and show how to append results from more than one simulation run. In addition, it will demonstrate the small overhead associated with running code coverage. You must be using ModelSim EE Special Edition for this lesson. The goals for this lesson will be to: • Run a simulation with Code Coverage ON and examine the coverage_summary window.
Simulating with Code Coverage This switch configures the test bench – the ringrtl.vhd file. Changing this entry in the text file causes two different tests to be run from the same test bench. 4 Compile top level block, test bench and configuration files. vcom ringrtl.vhd testring.vhd config_rtl.vhd (MENU: Design > Compile) 5 Use the vsim -coverage command to load the design configuration with Code Coverage. vsim -coverage work.
Simulating with Code Coverage Note that both testring.vhd and control.vhd are below 90% and, therefore, shown in red in the Coverage bar graph. 90% is the default coverage threshold. All coverage values below 90% will be shown red. The default coverage threshold can be changed with the Tcl control variable $PrefCoverage(cutoff). 8 Double-click on the control.vhd pathname to display the source code for control.vhd in the Source window.
Simulating with Code Coverage 10 Now, take note of how many times the clocked processes have been executed. Then edit the which_test.txt file to ensure that it reads "true = data_switch_test." 11 Restart the simulation with the changed flag so a different test is run on the circuit. restart -f 12 Restore the coverage data from the last simulation run so that its data can be appended to the last simulation run. coverage reload cover.dat 13 Run the simulator for 3msecs as before.
Simulating with Code Coverage Note that now both testring.vhd and control.vhd are above 95% and therefore shown is green. 15 Double-click on the control.vhd pathname to bring up the Source window. You can see from the values in the first column that the line hits from this run has been added to the ones from the last run. The number of times the clocked processes have been run have doubled.
Simulating with Code Coverage 16 Compile the lower level blocks with all optimizations switched off. This will cause more executable lines to be shown, and coverage data will be collected for the packages. vcom -O0 -noaccel std_logic_arith -noaccel std_logic_unsigned -noaccel std_logic_1164 control.vhd store.vhd retrieve.vhd 17 Compile top level blocks and configuration with optimizations switched off.
Lesson 11 - Finding names, and searching for values The goals for this lesson will be to: • Find items by name in tree windows. • Search for item values in the List and Wave windows. You can easily locate HDL item names and values within ModelSim’s windows. Start any of the lesson simulations to try out the Find and Search functions illustrated below.
The List Signal Search dialog box includes these options: You can locate values for the Signal Name: shown at the top of the dialog box. The search is based on these options (multiple Search Options may be selected): • Search Options: Ignore Glitches Ignore zero width glitches in VHDL signals and Verilog nets. • Search Options: Reverse Direction Search the list from bottom to top.
Finding names, and searching for values • Search Occurrences You can search for the n-th transition or the n-th match on value; Search Occurrences indicates the number of transitions or matches for which to search. • Search Value Valid only if Use signal value is selected; specifies the search value; must be formatted in the same radix as displayed. The result of your search is indicated at the bottom of the dialog box.
Finding names, and searching for values 11-102 ModelSim EE/SE Tutorial
Lesson 12 - Using the Wave window The goals for this lesson are: • Practice use of Wave window time cursors. • Practice the different methods for zooming the waveform display. • Practice using Wave window keyboard shortcuts. • Practice combining items into a virtual object.
Using the Wave window Using time cursors in the Wave window When the Wave window is first drawn, there is one cursor located at time zero. Clicking anywhere in the waveform display brings that cursor to the mouse location.You can add additional cursors to the waveform pane with the Cursor > Add Cursor menu selection (or the Add Cursor button shown below). The selected cursor is drawn as a bold solid line; all other cursors are drawn with thin solid lines.
Using the Wave window You can also move cursors to the next transition of a signal with these toolbar buttons: Find Previous Transition locate the previous signal value change for the selected signal Find Next Transition locate the next signal value change for the selected signal Zooming - changing the waveform display range Zooming lets you change the simulation range in the windowpane display. You can zoom with either the Zoom menu, toolbar buttons, mouse, keyboard, or VSIM commands.
Using the Wave window side of the desired zoom interval, press mouse button 1 and drag to the right. Release when the box has expanded to the right side of the desired zoom interval. • Zoom Range Brings up a dialog box that allows you to enter the beginning and ending times for a range of time units to be displayed.
Using the Wave window Syntax .wave.tree zoomrange f1 f2 Arguments f1 f2 Sets the waveform display to zoom from time f1 to f2, where f1 and f2 are floating point numbers.
Combining and grouping items in the Wave window The Wave window allows you to combine signals into buses or groups. Use the Edit > Combine menu selections to call up the Combine Selected Signals Dialog box. A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value. In the illustration below, four data signals have been combined to form a new bus called DATA1.
Using the Wave window A group is simply a container for any number of signals. It has no value, and the signals contained within it may be arranged in any order. In the illustration below, the signals counter/count, counter/clk, and counter/reset have been combined in a group called Counter. Notice that the Counter group has no value associated with it. The counter, clk and reset signals may be arranged in any order.
12-110 ModelSim EE/SE Tutorial
Index A Assertion errors 33 B Batch-mode simulation 41 Breakpoints 27 continuing simulation after 28 create new 60 creating 21 do command 12 DO files executing a DO file in batch-mode 41 using a DO file at startup 43 using the transcript as a DO file documentation 9 drag and drop 11 E C Code Coverage 93 coverage_summary window 94 reload 96 report 95 vsim -coverage command 94 Command history 11 Compile compile order 76 compile order of Verilog modules 62 mixed HDL design 75 projects 17 Verilog 59 coverag
of a Verilog design 65 Home page Model Technology’s home-page URL 9 Initialization file, see Project files ranked profile 90 report command 91 profile on command 83 Project files compile 17 create 14 creation wizard 15 edit 17 K Q I Keyboard shortcuts, Wave window 107 L Libraries creation and mapping 31 logical mapping 60 List window change display radix 67 placing top level Verilog signals in 63 Load Design 76 Load design 18, 24 M Macros see Do files modelsim.ini, see Project files .
applying stimulus to 25 display values with examine command 69 listing in region 25 placing top-level Verilog signals in the List and Wave window 63 specifying radix of 38 triggering listings for 37 Simulating code coverage 93 load design dialog box 18 with Performance Analyzer 81 Simulation batch-mode 41 executing commands at startup 43 Load Design dialog box 62 mixed VHDL/Verilog 73 saving results in log file 42 single-stepping 28 starting 32 Verilog 59 -view switch 42 -wav switch 42 solutions to the exam
