Technical data

vgencomp
80
-
ModelSim Command Reference ModelSim EE/PLUS Reference Manual
Examples
This example uses a Verilog module that is compiled into the
work
library. The
module begins as Verilog source code:
module top(i1, o1, o2, io1);
parameter width = 8;
parameter delay = 4.5;
parameter filename = "file.in";
input i1;
output [7:0] o1;
output [4:7] o2;
inout [width-1:0] io1;
endmodule
After compiling,
vgencomp
is invoked on the compiled module:
vgencomp top
and writes the following to stdout:
component top
generic(
width : integer := 8;
delay : real := 4.500000;
filename : string := "file.in"
);
port(
i1 : in std_logic;
o1 : out std_logic_vector(7 downto 0);
o2 : out std_logic_vector(4 to 7);
io1 : inout std_logic_vector
);
end component;
See "Component declaration" (p62) for more information on Verilog component
declaration.