Technical data

vgencomp
ModelSim EE/PLUS Reference Manual ModelSim Command Reference
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vgencomp
Once a Verilog module is compiled into a library, you can use the
vgencomp
command to write its equivalent VHDL component declaration to standard output.
Optional switches allow you to generate bit or vl_logic port types; std_logic port
types are generated by default.
Syntax
vgencomp
[ -help ] [ -<library_name>][-s][-b]
[ -v ] <module_name>
Arguments
-help
Displays the command’s options and arguments. Optional.
-<library_name>
Specifies the pathname of the working library. If not specified, the default library
work
is
used. Optional.
-b
Causes
vgencomp
to generate bit port types. Optional.
-s
Used for the explicit declaration of default std_logic port types. Optional.
-v
Causes
vgencomp
to generate vl_logic port types. Optional.
<module_name>
Specifies the name of Verilog module to be accessed. Required.