Technical data

Verilog instantiation of VHDL design units
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Mixed VHDL and Verilog Designs ModelSim EE/PLUS Reference Manual
Port associations may be named or positional. Use the same port names and port
positions that appear in the entity.
Named port associations
Named port associations
are not
case sensitive – unless a VHDL port name is an
extended identifier (1076-1993). If the VHDL port is an extended identifier, the
association is case sensitive and the VHDL identifier’s leading and trailing
backslashes are removed before comparison.
Generic associations are provided via the module instance parameter value list.
List the values in the same order that the generics appear in the entity. The
defparam
statement is not allowed for setting generic values.
An entity name is not case sensitive in Verilog instantiations. The entity default
architecture is selected from the work library unless specified otherwise.
Verilog does not have the concept of architectures or libraries, so the escaped
identifier is employed to provide an extended form of instantiation:
\mylib.entity(arch) u1 (a, b, c);
\mylib.entity u1 (a, b, c);
\entity(arch) u1 (a, b, c);
If the escaped identifier takes the form of one of the above and is not the name of
a design unit in the work library, then the instantiation is broken down as follows:
• library = mylib
• design unit = entity
• architecture = arch
SDF annotation
A mixed VHDL/Verilog design can also be annotated with SDF. See "SDF for
Mixed VHDL and Verilog Designs" (p447) for more information.