Technical data

Verilog instantiation of VHDL design units

ModelSim EE/PLUS Reference Manual Mixed VHDL and Verilog Designs

A port clause is generated if the module has ports. A corresponding VHDL port is

defined for each named Verilog port.

The VHDL port type is selected by the user from among bit, std_logic, and

vl_logic. If the Verilog port has a range, then the VHDL port type is bit_vector,

std_logic_vector, or vl_logic_vector. If the range does not depend on parameters,

then the vector type will be constrained accordingly, otherwise it will be

unconstrained.

Examples

Configuration declarations are allowed to reference Verilog modules in the entity

aspects of component configurations. However, the configuration declaration

cannot extend into a Verilog instance to configure the instantiations within the

Verilog module.

Verilog instantiation of VHDL design units

You can reference a VHDL entity or configuration from Verilog as though the

design unit is a module of the same name (in lower case).

VHDL instantiation criteria

A VHDL design unit may be instantiated from Verilog if it meets the following

criteria:

• The design unit is an entity/architecture pair or a configuration declaration.

• The entity ports are of type bit, bit_vector, std_ulogic, std_ulogic_vector,

vl_ulogic, vl_ulogic_vector, or their subtypes. The port clause may have any

mix of these types.

• The generics are of type integer, real, time, physical, enumeration, or string.

String is the only composite type allowed.

Verilo

port VHDL port

input p1; p1 : in std_logic;

output [7:0] p2; p2 : out std_logic_vector(7 downto 0);

output [4:7] p3; p3 : out std_logic_vector(4 to 7);

inout [width-1:0] p4; p4 : inout std_logic_vector;